The debugger in the ARM® Development Studio 5 (DS-5™) is able to debug both SMP and AMP system designs, either by traditional JTAG-based debug hardware such as DSTREAM, or via the new CMSIS-DAP over USB. CMSIS-DAP is an open firmware standard which allows any Cortex-M series devices with USB capabilities to connect to a host debugger. A second Cortex-M4 on Freescale's Vybrid board, when programmed with the CMSIS-DAP firmware, enables both processors in Vybrid to be connected to DS-5 Debugger using only a USB cable. This includes not only regular source-level debug, but also collection of a trace of instruction execution via the on-chip Embedded Trace Buffers (ETB) - no other debug hardware is needed.
In this blog I’ll show you how to debug and trace code at source-level, running both Cortex-M4 and Cortex-A5 processors on a Vybrid board and using just CMSIS-DAP over USB with DS-5 Debugger. In case you just can’t wait until you read this through, here is the video showing the setup.
First launch DS-5 Debugger on a host machine. If you do not have the DS-5 toolchain installed on your machine, you can download a free 30-day evaluation license. Once you are set up, connect the Vybrid Tower with a USB cable. The USB cable provides both power for the Vybrid Tower, and debug control information between debugger and target. We can now create debug connections to either the A5, or to the M4, or to both simultaneously! To create a debug connection to the A5, open the Debug Configuration dialog (Run->Debug Configurations), create a new connection and give it a name (let's call it "Vybrid A5 Bare Metal"), and select the target (Freescale Vybrid). This is just one of more than one hundred ready-made platform configurations that are already directly supported by DS-5 Debugger. Then select the debug operation, either Bare Metal Debug, Linux Application Debug or Linux Kernel and/or Device Driver Debug. To start with, we’ll use Bare Metal Debug -> Debug Cortex-A5 via CMSIS-DAP.
If you have some code to download, you can specify the executable file in the Files tab. In the Debugger tab, select to Connect only, Debug from entry point, or debug from main. Finally, press Debug. The DS-5 Debugger will then establish a debug connection to the target, download the code to the target, and load the debugging information to allow you to debug the code at source level. You can then run, stop, set breakpoints, view variables, view registers, view disassembly, view memory, and so on in the normal way.
To create a debug connection to the Cortex-M4, open the Debug Configuration dialog, create a new connection and give it a name (let's call it "Vybrid M4 Bare Metal"), and select the target (again, Freescale Vybrid) and debug operation (again, Bare Metal Debug -> Debug Cortex-M4 via CMSIS-DAP). Configure the Files tab and Debugger tab as required, then press Debug to connect and start debugging.
The Cortex-M4 clock is not enabled by default when the Vybrid board is reset. It can be enabled by executing a certain instruction sequence on the Cortex-A5, but if this is not present or the Cortex-A5 is not active, DS-5 Debugger can enable the CortexM4 clock for you, so that you can then run and debug code on the Cortex-M4 on its own. To tell DS-5 Debugger to enable the clock on connection, return to the Debug Configuration dialog for the Cortex-A5 or Cortex-M4 connection you made earlier, then click on the DTSL Options “Edit…” button. The acronym “DTSL” stands for “Debug and Trace Services Layer” - a powerful, scriptable (Jython-based) interface that allows the user to configure platforms in various ways. In the DTSL Configuration dialog, tick “Enable Cortex-M4 clock”.
When it is first started, DS-5 Debugger shows just one Registers view, one Disassembly view, and one Memory view. To save on screen real estate, you can use just one instance of these views and switch between Cortex-A5 and Cortex-M4 contexts by selecting the current processor in the Debug Control view. Alternatively, you can open new Registers, Disassembly, and Memory views, and associate these with a specific processor, using the view/connection linkage feature. In this way, the state of both processors is visible side-by-side on screen at the same time. Notice in the two Disassembly views below that the Cortex-A5 code was compiled to 32-bit ARM instructions and is being run in Secure state (“S:”) , and the Cortex-M4 disassembly shows 16/32-bit Thumb-2 instructions, because the Cortex-M seriesfamily supports Thumb-2 only.
The two processors share some memory space in the memory map, so this region can be used to implement, for example, mailboxes to allow the two processors to exchange information. Both processors also have 16 semaphore peripherals to marshall access to these shared areas. To visualise and debug shared memory accesses, you can set a hardware watchpoint on a word in memory, so that program execution will stop when that address is read from and/or written to. To do this, in this Variables view, right-click on a shared variable, select Toggle Watchpoint, select the required access type (for example, a write), and then click OK. Do this for both processors. Now run the code, and when either processor tries to write to this location, program execution will stop. Alternatively, use the “watch” command in the CLI, for example, if you know its absolute address, use “watch *0x3F020000”.
If you want to obtain a trace of instruction execution for either the Cortex-A5 or the Cortex-M4, you can do so without needing any other debug hardware via the on-chip Embedded Trace Buffers (ETB). To enable this, disconnect from the target, and return to the Debug Configuration dialog for the connection you made earlier, then click on the DTSL Options “Edit…” button. In the DTSL Configuration dialog, tick “Enable Cortex-A5 core trace” and/or “Enable Cortex-M4 core trace” as required, and select “On Chip Trace Buffer (ETB)” for each.
Press Debug to reconnect, then run some code until it reaches a breakpoint or you press Stop. The Trace view then displays the sequence of instructions the core executed that was captured in the ETB, and the functions they are associated with. Trace can be obtained from both processors and, using the view/connection linkage feature, both traces can be placed side-by-side on screen.
In summary, we have seen that the features of DS-5 Debugger, such as CMSIS-DAP over USB, multiple processor connections and flexible DTSL support, make it easy to debug and trace systems containing different types of processors. These features open up avenues to low-cost development and optimization of systems designed around the new breed of ARM-based AMP devices such as Freescale’s Vybrid family of controllers.
Learn more about ARM Development Studio 5.
Stephen Theobald, Principal Applications Engineer, ARM, Stephen is part of the DS-5 Applications team that puts the ARM tools through their paces and uses them to create example software to demonstrate features of the tools and promote their usage. Stephen also worked for several years in ARM's Product Support group, so is well used to helping customers make the best use of ARM tools.
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