Round 3: RISC vs. CISC in the PostPC Era
The importance of maintaining the sequential programming model combined with the increasingly abundant number of transistors from Moore’s Law led, in my view, to wretched excess in computer design. Measured by performance per transistor or by performance per watt, the designs of the late 1990s and early 2000s were some of the least efficient microprocessors ever built. This lavishness was acceptable for PCs, where binary compatibility was paramount and cost and battery life were less important, but performance was delivered more by brute force than by elegance.
However, these excessive designs are not a good match to the smartphones and tablets of the PostPC era. RISC dominates these “Personal Mobile Devices,” because
- It’s a new software stack and software distribution is via the “App Store model” or the browser, which lessens the conventional obsession with binary compatibility.
- RISC designs are more energy efficient.
- RISC designs are smaller and thus cheaper.
The table below from Microprocessor Report supports these last two claims:
Comparing performance per megahertz, x86 is 4% - 8% faster than ARM or MIPS. More significantly, this table suggests ARM and MIPS have 40% - 50% better energy per MHz and their size is a factor of 3X to 4X smaller than x86.
Independent of these architectural battles, Personal Mobile Devices rely on “Systems on a Chip” to reduce size, improve energy, and to lower costs. If processors are available as IP blocks, any company can create a single SOC rather than use many separate chips on a printed circuit board, as is the case with PCs. Thus far, there is no serious x86 IP competitor to the many fine RISC IP options, so SOCs based on x86 can only come from AMD or Intel.
RISC vs. CISC in the Client and in the Server of the PostPC Era
If Personal Mobile Devices are the clients of the PostPC Era, then Cloud Computing is the server. Virtually all PostPC apps will have one foot in the client and one in the cloud. While RISC has a substantial lead in PMDs, CISC leads in the commodity server market that is the building block of Cloud Computing.
Interestingly, binary compatibility again plays a small role in Cloud Computing, and cost and energy efficiency again play a much larger role than in PCs. Moreover, when you acquire 100,000 servers at a time to build a Warehouse Scale Computer, custom microprocessors could make sense. RISC competitors would need 64-bit addresses, ECC-protected memory, and good virtual machine support to compete in the Cloud, but the door is not slammed shut as it was in the PC Era.
Conclusion: RISC Reascendancy for Round 3
Note that the volume is on the side of PMDs in the PostPC Era: there will surely be 100 chips built for PMDs for every chip made for Cloud Computing. For 2010, even if you include the whole PC market—which you would expect to fade eventually in the PostPC Era—the RISC chips still outnumber CISC chips by 10:1 to 15:1.
Depending on your perspective, a happy result of the latest round of the RISC-CISC Wars is RISC reascendancy.
 “Dawn of a New Day,” Ray Ozzie, http://ozzie.net/doc...n-of-a-new-day/, October 28, 2010.
 “Broadcom Shows Off New CPU,” Linley Gwennap, Microprocessor Report, November 22, 2010.
David Patterson has been Professor of Computer Science at UC Berkeley since 1977. He is one of the pioneers of Reduced Instruction Set Computers, Redundant Arrays of Inexpensive Disks, and Network of Workstations in addition to being co-author of two widely-used textbooks on Computer Architecture, now in their 4th editions. He is a member of the US National Academy of Engineering, the US National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. Recently, while exploring the perceived value of Personal Mobile Devices in the PostPC Era, he made the shocking discovery that iPads make excellent Christmas presents for your adult children!
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