ARM Community: Embedded Live: Embedded Programmers' Guide to ARM’s Cortex-M Architecture - ARM Community

The majority of supporting material around the new generation of ARM® Cortex™-M architectures (M0, M3 & M4), unsurprisingly, focuses heavily on the key hardware specifics of the microcontroller core, with most coding examples being in THUMB-2 assembler. However the majority of programming for the Cortex family will be in the C programming language (recently a VDC report showed C is still head-and-shoulders above other languages for embedded programming. As an embedded software engineer, you can take advantage of many useful technologies and products of the Cortex-M that makes it truly an excellent target environment including ARM’s CMSIS’ support package for peripheral registers and exception vectors, easy debug environment, extensive RTOS support and multiple evaluation kits.

Embedded Live tutorial

Want more? I’ll be presenting a more detail at a half-day tutorial entitled “EMBEDDED PROGRAMMERS' GUIDE TO THE ARM CORTEX-M ARCHITECTURE” at Embedded Live 2010 that class looks at all the really useful features added to the Cortex-M that are highlighted below.

Signed and unsigned integer instructions

As a simple example many embedded processors do not support integer division in hardware (e.g. ARM7), so division typically handled by an intrinsic library function call or compiler ‘tricks’



The new Cortex-M3 has new signed and unsigned integer division instructions, that can also support modulo operation ( x % y )





There are many other features that I shall cover including unaligned-transfers, bit-banding and the new improved interrupt support architecture (NVIC).

However, there are three other significant supporting technologies that really help the software engineer.
1. Cortex Microcontroller Software Interface Standard (CMSIS)
2. Debug Support
3. RTOS Support

CMSIS support package for peripheral registers and exception vectors

Simply put, the CMSIS is a collection of source files (.c, .h and assembler) to create a minimal support package for Cortex-M series processors. Very usefully, it defines a common way to access peripheral registers and define exception vectors. It also defines the register names of the Core Peripherals and the names of the Core Exception Vectors. So, instead of having to spend time and effort defining structs for register definitions for onboard devices (or hoping you development environment has already done this for you) you can be assured that they already exist. For example, the NXP LPC17xx family of microcontrollers support a watchdog timer. Being CMSIS compliant, then the supplied header LPC17xx.h defines the register layout and necessary #defines:



Easy and affordable debug support

JTAG units, such as the Keil ULINK, have made target programming and source-level debug very affordable. However, for small pin count micros, the 4-wire JTAG is seen as quite expensive option (in terms of pure pin-count). As part of the Cortex-M core is support for a new Serial-Wire Debug interface. The advantage being that it only requires 2-wires, which makes it very easy and affordable to support debug for microcontrollers with low pin counts.



At the other end of the spectrum, ARM have added the option for an Embedded Trace Macro (ETM) unit, which allows features such as debug of events in real-time systems where the target cannot be halted and software profiling and code coverage.

Extensive RTOS Support with MPUs and MMUs

For someone who has a long background in Real-Time Operating Systems, I was very interested to discover how ARM has made it simpler and easier for an RTOS vendor to support the Cortex-M. As you can guess CMSIS is a huge step forward, as it means once an RTOS has been ported using CMSIS, the core aspects will work on, say, all Cortex-M3 implementations.

As a simple example, pretty much all RTOS require a time-frame reference (the “tick” timer) for timeouts and delays, etc. ARM has integrated this directly into the core (called Systick) rather than each silicon vendor having to implement their own count-up or count-down variant. There are already 20+ RTOSs running on the Cortex-M.

Also, as an optional part of the Cortex-M3/M4 core is a Memory Protection Unit (MPU). An RTOS can make use of this to create a safer multitasking platform without the expense of a full-blow Memory Management Unit (MMU).



Multiple evaluation kits for easy access

Finally, what makes the Cortex-M so attractive from a embedded software engineers perspective is to abundance of low cost evaluation kit, such as mbed, LPCXpresso, STM32 Value line Discovery, Energy Micro, and Actel’s SmartFusion to name just a small selection.

I hope to see you at Embedded Live 2010. If so please come and say hello.

Guest Partner Blogger:
Niall Cooling, Director, Feabhas, Feabhas are the UK’s leading independent provider of training for real-time embedded systems development. Niall lectures in many topics for Feabhas, including C and C++ for Real-Time Embedded Systems based on ARM microcontrollers. Niall has delivered training and provides mentoring to a wide variety of electronics companies including telecom, automotive, semiconductor, aerospace and defence. Niall is a Chartered Engineer.

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