ARM Community: SoC Design - ARM Community

I hate reading manuals. Maybe it’s a guy thing or maybe it’s the engineer in me, but it’s pretty rare that I’ll bring home a shiny new device and then sit down and read the manual. Give me a few pictures or examples on how something should be used and I’m good to go. Not surprisingly, a lot of customers take this same approach with our software products. Immediately after installation they’ll start things up and look around for an examples directory long before they’ll ever click on the “Help” button.

This approach works well for a lot of tasks but when it comes to more complex tasks that example needs to be very sophisticated to be of value. System on chip (SoC) performance analysis, certainly meets that “complex task” threshold. The best way to analyze the performance of an SoC before it is built is by using a virtual prototype. Before any performance analysis work can be performed however, there is a long list of tasks to be performed. Models need to be assembled and configured for all of the important design elements, or even written if the models don’t already exist. These models need to be pulled together into a system configuration which matches the end design. Finally, software must be written to initialize all of the components in the system and then generate some meaningful traffic. Hopefully your virtual prototyping tool has some good data visualization tools. If not, you can add data extract...

Transcending “Reality” with Virtual Platforms
"Virtual reality is the first step in a grand adventure into the landscape of the imagination.”
--Communication in the Age of Virtual Reality by Frank Biocca, Taeyong Kim and Mark Levy

So what is the reality, and virtual reality, for embedded software developers? Virtual platforms will be increasingly important, especially for multi-core designs. The April 2012 EE Times Embedded Software Survey reported that 33% of software developers say virtual platforms are becoming more important to accelerate their schedules.

Why Use Virtual Platforms?
When hardware is not available, you can still start software development early and with confidence. Virtual platforms can be programming-model hardware accurate, and allow you to run the exact binary you code for the real device. They deliver the level of abstraction and performance needed to run operating systems and application software and integrate external system components and interfaces.

Even when hardware is available, virtual platforms offer significant advantages. Virtual platform changes can be instant...

If you've watched any sporting event on television lately, you've seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time from a single vantage point. But watching at home on television, we get the luxury of viewing multiple replays of events in question in high-definition super-slow-motion, one frame at a time, and even in reverse. We also get to see many different views of these controversial events, from the front, the back, the side, up close, or far away. Sometimes it seems there must be twenty different cameras at every sporting event.

Wouldn't it be nice if you could apply this same principle to simulation and emulation runs of your ARM® Cortex™-A series processor-based SoC designs? What if you had instant replay from multiple viewing angles in your functional verification toolbox? It turns out that such a technology indeed exists, and it's called "Codelink Replay".

Mentor Graphics’ ...

Power, performance and area or “PPA,” as it is called, has become a universally interesting topic to system-on-chip (SoC) designers around the world. Atrenta – an ARM Connected Community Partner and a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries – showcased a new and innovative design flow for early PPA estimation at last year’s ARM TechCon.

Design complexity now demands that all aspects of the design be co-optimized. If you reduce power, you will impact performance and area and so on. A holistic approach that balances all requirements of the chip is needed to deploy SoCs successfully.

Improving PPA by analyzing interconnect fabric earlier
Anyone will tell you that the interconnect...

Co-authored by Stephen Pateras, Mentor Product Marketing Director, Silicon Test
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Memory Built-In Self-Test (BIST) has existed for as long as there have been modern SoCs. With today’s advanced SoCs containing literally hundreds and even thousands of SRAM memories, clustered in many memory subsystems throughout the SoC, both memory BIST as well as Built-In-Self-Repair (BISR) technology are increasingly important to insure the highest possible yield. System-on-chip designs are tailored for the optimal power, performance, area (PPA) and cost for a specific target application. To meet these increasingly challenging goals, designers are implementing solutions using multiple power domains, allowing the memory to run at high speed while conserving power in the periphery. These factors, combined with the different types of memories, including high density and high speed; single port, multi-port, register files and ROMs add to the complex task of ensuring the SoC performs to specification, and doesn’t limit yield in high volume production.

ARM has teamed up with ...

Find out more about what ARM’s Processor Optimization Pack (POP) is and its advantages.

Like many people who work in high tech, from time to time I’ve had trouble explaining my profession to family and friends. Unless you are pretty tech savvy it is hard to understand exactly what a SoC engineer does everyday. The other day I was driving in my car dropping my son off at Cub Scouts when he asked me, “Dad what do you do at work?” It’s the kind of question that comes out of the blue and you struggle to answer. I paused for a few moments searching for a simplified answer and responded “I make ARM processors go faster.” He seemed satisfied with that answer, and quickly became distracted when his favorite song came on the radio; when you’re a seven year old you just love singing in the car!

When I joined ARM in 1997 I was a SoC engineer in ARM’s consulting group, the group’s main focus was to enable a Partner to get to market faster by taking advantage of AR...

The Jasper User Group Meeting was held on November 8 & 9 and was full of presentations on the diverse ways that users are applying formal techniques – some in areas where never before thought possible. Paul Martin from ARM was one of those users who presented on this topic. ARM discussed how modern multi-core processors now require much more sophisticated cache control than before, ensuring that all devices in the system have the same view of shared data, known as cache coherency. ARM in particular has created some quite sophisticated protocols, AXI Coherency Extensions (ACE), under the AMBA 4 umbrella, that they announced at DAC.

The need to move cache management to hardware
In the old days, cache coherency management was largely done in software, invalidating large parts of the cache to ensure no stale data could get accessed, and forcing the cache to gradually be reloaded from main memory. There are several reasons why this is no longer appropr...

In text books, academia, and articles there is a consensus that to ensure the material is understood it helps to define terminology. I will define Low VDD in the context of a low power supply being connected to my Integrated Circuit of Choice. It does not necessarily imply low power or low energy which is where I think we, in the IP business need to continue directing our focus.

Mathematically, yes power, both dynamic and static, are functions of “V” and you can find enough literature out there with many equations of sorts. So in theory, the lower we make the VDD the better, right? Well it’s not just about V or Vmin, it’s also about other entities like t(time) and RC (resistance and capacitance). If you operate at 0.6V and it takes you twice as long to switch your circuit you will be consuming potentially more crowbar current as you arduously try to switch, so in the end you haven’t really saved that much on either your battery or your PG&E bill. And hiding behind the “t” issue is the RC. It will hinder the propagation of signals through your elegantly designed circuits, boards and systems. So unless you have a lossless system, which doesn’t exist, RC will always be there slowing you down - interfering with the ideal world that Lowering VDD is your solution to lowering power. To make matters worse, RC does not often scale as much as we would like. Another issue is it’s not just about wire RC, but ...

High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM’s big.LITTLE processing. In case you missed the announcements, the big.LITTLE technology offers an innovative way to run the ‘always on’ tasks on the highly efficient Cortex™-A7 processor, while the high performance and responsive applications are predominantly executed on the Cortex™-A15 processor. So what does this have to do with AMBA 4? Well AMBA 4 ACE and the CoreLink™ CCI-400 Cache Coherent Interconnect offer the critical glue to join these processors together into a big.LITTLE multi-processing (MP) system. Let me explain…

Earlier this year ARM announced the public release of the AMBA 4 phase 2 specification including AC...

At the TSMC Open Innovation Platform (OIP) forum in San Jose this week Mike Inglis, the General Manager of the Processor Division at ARM, presented a keynote speech succinctly titled “Enabling Smart System Design Through Collaboration, Optimization and Scalability”. This presentation outlined many of the challenges faced by silicon developers around the globe, and noted some solutions that can help reduce these design pains.

For me, the most important aspect of this talk was the public announcement of the availability of a new Cortex™-A5 Hard Macro for the TSMC 40nm Low Power node (40LP) which can achieve a whopping speed of over 1GHz in a tiny footprint of just 1mm2.

This Hard Macro is based on a uni-processor implementation of the Cortex-A5, and includes NEON™, Flo...

I’ve recently realized just how similar mechanical and electronic engineering are when it comes to energy conservation. You see, I've recently begun construction of an energy-efficient, Frank-Lloyd Wright -inspired architect-designed house in Lakeway, Texas just outside Austin where the ARM US engineering team is based. We're coming to the end of a long and very hot summer here in Austin so naturally I spent quite an amount of time researching energy-efficient solutions to air-conditioning (A/C). To minimize energy consumption we're putting in an unusual heating and air-conditioning system which consists of eight ceiling cassettes all connected via refrigerant pipes to a single, external electronic inverter-controlled infinitely variable compressor. Each ceiling cassette A/C outlet can be individually controlled from an iPhone App from anywhere in the world and can run at any one of four speeds. Instead of pumping air around the house in ducts as with a traditional A/C system we pump refrigerant around in pipes, which is more efficient as it wastes less energy pumping. The total power output capacity of the eight outlets can total up to 130% of the maximum compressor output, but obviously you can't have all eight outlets on full blast at the same time.

In explaining the system to my friend and ARM colleague ...

Thank goodness for the new packetization, virtual networking and clock gating features of the ARM CoreLink NIC-400. I’m fed up with hearing about spurious comparisons between a single humungous crossbar switch and NoC solutions. No design of any complexity uses a single cross bar switch! Modern SoC designs integrate large numbers of IP cores supporting the de facto industry standard AMBA AXI interface (open to all) using a network of small switches to allow very high operating frequencies and reduced routing congestion while still maintaining very low latencies and simplicity and flexibility of design.

Smart customers evaluate the alternatives to compare performance (bandwidths and latencies) vs. cost in terms of silicon area, routing congestion, power and price.

Packetization is great to increase wire utilization, but comes with a packetization/depacketization overhead that costs latency, gates and power. So should be used where it helps most to cross long distances with multi-cycle timings, f...

As Moore’s Law continues to drive the semiconductor industry to smaller and faster transistors, 40nm chips are state-of-the-art, 32nm/28nm cores are right around the corner, and companies are now planning their 20nm flows, methodologies, and products. Foundries have been working tirelessly over the last few generations, adding new, sophisticated steps to the manufacturing process to prolong the power and performance scaling that has defined the semiconductor industry over the last 30 years.

Around the 40nm node, manufacturers began adding in new materials to permanently put silicon transistors under compressive or tensile stress. By adding the correct type of material and inducing the right type of stress, foundries now provide increased carrier mobility in NMOS and PMOS devices. At 32nm/28nm, high-k metal gates are being introduced into the manufacturing flow of all the top foundries. High-k metal gates reduce transistor leakage without reducing performance, and enable further oxide scaling in fu...

Last week ARM participated in the GLOBALFOUNDRIES 2011 Global Technology Conference (GTC11), ARM was involved in two notable panel sessions that covered a range of important industry issues. I wanted to share with you a few highlights of those discussions.

The first is the annual CEO panel, something that is becoming a GTC tradition. This one was entitled “Design Enablement Challenges and Future Solutions”. At this event, right after lunch, CEO’s, get together to talk about industry trends. ARM participated in the panel last year as well, with Simon Segars (EVP/GM of ARM’s Physical IP Division) representing ARM along with nearly the same other panelists. Also like last year, the panel was moderated by Mojy Chian from GLOBALFOUNDRIES, their Senior VP of Design Enablement. The panelists were:
Warren East, CEO, ARM...

There is an old saying that no matter where you are in the world you are never more than three feet away from a spider. I can’t tell you if this is true, although my wife hopes it isn’t. However it is probably a fact of life that you are never more than three feet away from a silicon chip manufactured on a mainstream technology process (250nm-90nm). Take a look around you right now. The computer screen you are reading this blog on is driven by display drivers manufactured on a mainstream technology node. That mobile phone you just used has several chips manufactured on mainstream nodes for battery management, power control and display functions. Your GPS device, tablet, coffee maker, microwave oven, PMP, video game player, and even the toys your kids are playing with are all powered by mainstream technology. As more of these products incorporate ARM-based microcontroller and microprocessors combined with wireless technology the application goes beyond an internet of ...

If you missed DAC, then you missed the seminar on cache coherency and verification of cache coherency given by ARM and Jasper. Learn how to overcome the typical challenges of capturing the intent, reviewing possible scenarios and how to correct errors in functional terms as they relate to the specification.

The seminar (on-line recording) kicked off with a discussion on how the implementation of hardware-based coherency in high-performance parallel compute environments is not new. The seminar quickly revealed that architects and designers of high-performance, heterogeneous, embedded multi-processing SoC’s, particularly those with one or more caches and when many masters share a single area of memory, now require robust specifications, design & verification tools and systems IP, to ensure their devices minimize off-chip memory transactions, while maximizing performance and power efficiency. The seminar then went on to explain why ARM has chosen to include Coherency Extensions...

Having chosen the optimal implementation, as described in the previous blog, we now turned our attention to power management.

Simulations of Elba at this point of the program were starting to supply some rather noticeable power levels for the processor, especially at the design corner we were most familiar with. The worst case design corner is a statistical point across the variations that you could potentially see from a silicon process at a temperature that is assumed to not exist. Remember, ARM's primary market was mobile devices, so for these devices a manufacturer wanted to know that every chip delivered from the fab would achieve the defined performance. So speed would always be defined by the statistically slowest piece of silicon, and the power would be defined by the statistically fastest and hottest piece of silicon – neither of which would ever exist in reality, but allowed the manufacturer to maximise device yield without testing each part for its performance. You may know that around 1 billion phones were sold last year – and that would be a lot of cost to ‘speed-bin’ parts across that market.

There are various ways to speed-bin a SoC, but basically the two main o...

The 48th DAC was held in San Diego this year and whenever DAC is not in Silicon Valley there is always a concern about how many people are going to show up. Fortunately the sun shone on San Diego and there seemed to be a good number of people in attendance.

This year, for only the second time in history, there was an ARM booth at DAC. In previous years we have shown demos within our partners’ booths but this year we had our own space as well as working with our partners as usual. One of the messages we were promoting at DAC the need for a complete system solution approach to design, as opposed a collection of components designed in isolation of each other. We call this Smarter Systems Solutions and John Heinlein gave a presentation on this subject on the Chip Estimate booth. During DAC, ARM also ...

Are you using a mobile device? Chances are you’re probably reading this blog post on one. You’re also probably reading this with the confidence that your device is doing what you intend it to do. As consumers, we place a lot of demands on not only our mobile devices but also the rest of our personal electronics. We want them to perform all sorts of tasks efficiently, accurately, and with minimal power consumption. As an engineer, you’re aware of the complex embedded SoC’s used in your device to make sure that it does what’s intended. Today’s embedded SoC’s are high performance, heterogeneous, and multi-processing systems.

In the future, most of these embedded SoC’s are likely to contain multiple caches that share a single memory resource. At a high level, cache coherency means that two caches cannot have same cache line in a dirty state and that if a cache contains a cache line in a unique state, that line must not be in another cache. In addition, at least one transaction must always be able make forward progress (no deadlock.) To prevent these cache coherency issues, ARM has included cache coherence extensions in their AMBA 4 protocol specification.

While this is a tremendou...