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Virtual Platforms Accelerate Embedded Software Development

Transcending “Reality” with Virtual Platforms
"Virtual reality is the first step in a grand adventure into the landscape of the imagination.”
--Communication in the Age of Virtual Reality by Frank Biocca, Taeyong Kim and Mark Levy

So what is the reality, and virtual reality, for embedded software developers? Virtual platforms will be increasingly important, especially for multi-core designs. The April 2012 EE Times Embedded Software Survey reported that 33% of software developers say virtual platforms are becoming more important to accelerate their schedules.

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Source: UBM Electronics -- Embedded.com & EE Times.


Why Use Virtual Platforms?
When hardware is not available, you can still start software development early and with confidence. Virtual platforms can be programming-model hardware accurate, and allow you to run the exact binary you code for the real device. They deliver the level of abstraction and performance needed to run operating systems and application software and integrate external system components and interfaces.

Even when hardware is available, virtual platforms offer significant advantages. Virtual platform changes can be instant...

Spreading the Multicore Message 'Down Under'

ARM is heading to Multicore World 2012 to discuss ARM MPCore solutions and grow the development ecosystem in New Zealand.

If you were to ask most people what New Zealand is famous for, you’d probably hear it has more sheep than people, suggesting that the most that small country down-under can offer is open spaces and woolly clothing – how wrong.

Later this month, the balance will be put a little out of shape, starting on the 27th March for two days a number of international speakers and researchers and I will be taking time to specifically travel to New Zealand to address and participate within their growing community of businesses and technology innovators addressing the international challenge of multicore at Multicore World 2012.

ARM today has very little of its development ecosystem located in the southern hemisphere, however this opportunity to inform the community about the ARM MPCore solutions and vision was too good to be missed. As such, I will be travelling fr...

Streamlining the migration to an ARM processor based platform

Now available design strategies and documentation to ease the migration to an ARM platform - From one programmer to another.

You could say I’m an “Acorn boy” – I cut my programming teeth on personal computers from Acorn in the late ‘70s and early ‘80s. All were based around the 6502 and, perhaps because, it’s where I started, I still look on that processor with great affection. I’ve used many other devices in my 25-year career in embedded software – 6502, 6809, 6811, Z80, 68000, 8051, 8086 to name a few. For the last eleven years, I’ve worked at ARM and have worked almost exclusively with various flavours of the ARM architecture. I had worked with ARM processors before that, though. In my life as a consultant software developer, I was part of the team which ported BSD Uni...

将大小计算引擎完美地整合在-起 - ARM Cortex-A7

今天,ARM Cortex-A7 的隆重推出…标志着 big.Little 处理架构的最终实现!

我驾驶着一辆节能型的本田飞度行驶在 20 英里的市区上班途中。有时我会突发奇想,希望在自己的座驾上安装一个更快的引擎,但大部分时间我还是对自己驾驶的节能车辆感到很满意。但我必须承认我曾抗拒换一辆经济型轿车;我时常梦想自己拥有像保时捷或宝马车那样的性能,但只希望在驾车的小部分时间里拥有这种卓越的性能。如果我能驾驶一辆平均能效保持在四缸引擎范围内,而在需要最高性能的片刻可迅速切换到高性能的涡轮增压式 V8 引擎汽车,那该有多好啊?如果平均燃油能效接近于 4 缸引擎,而最高性能接近于涡轮增压式 V8 引擎的性能,会怎样?
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Combining large and small compute engines - ARM Cortex-A7

Today the ARM Cortex-A7 processor was announced…the power of big.Little processing is finally realized!

I drive a Honda Fit, mainly for the fuel efficiency, on a 20 mile city street commute. Sometimes I wish my car had a faster engine, but most of the time I’m happy to drive for high gas mileage. But I have to say I was a reluctant convert to economy cars; I often find myself longing for the performance of a Porsche or BMW, but I only really want that performance a small percentage of the time I’m driving. Wouldn’t it be great if it were possible to drive a car with the average efficiency of a 4-cylinder engine, a car that could switch to a high performance of a turbocharged V8 engine for the small percentage of time you actually wanted peak performance? What if the average fuel economy was closer to the 4-cylinder and the peak performance was closer to that of the turbo V8?

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Stirring up debate at GTC 2011

Last week ARM participated in the GLOBALFOUNDRIES 2011 Global Technology Conference (GTC11), ARM was involved in two notable panel sessions that covered a range of important industry issues. I wanted to share with you a few highlights of those discussions.

The first is the annual CEO panel, something that is becoming a GTC tradition. This one was entitled “Design Enablement Challenges and Future Solutions”. At this event, right after lunch, CEO’s, get together to talk about industry trends. ARM participated in the panel last year as well, with Simon Segars (EVP/GM of ARM’s Physical IP Division) representing ARM along with nearly the same other panelists. Also like last year, the panel was moderated by Mojy Chian from GLOBALFOUNDRIES, their Senior VP of Design Enablement. The panelists were:
Warren East, CEO, ARM...

Cache Coherency and Verification Seminar at DAC – Now Online!

If you missed DAC, then you missed the seminar on cache coherency and verification of cache coherency given by ARM and Jasper. Learn how to overcome the typical challenges of capturing the intent, reviewing possible scenarios and how to correct errors in functional terms as they relate to the specification.

The seminar (on-line recording) kicked off with a discussion on how the implementation of hardware-based coherency in high-performance parallel compute environments is not new. The seminar quickly revealed that architects and designers of high-performance, heterogeneous, embedded multi-processing SoC’s, particularly those with one or more caches and when many masters share a single area of memory, now require robust specifications, design & verification tools and systems IP, to ensure their devices minimize off-chip memory transactions, while maximizing performance and power efficiency. The seminar then went on to explain why ARM has chosen to include Coherency Extensions...

Elba - Bringing it all together

In the previous three blogs (Parts 1, 2 and 3) I’ve outlined the background and key decisions involved in the development and implementation of the Elba testchip. Now we’ll look at the final steps taken to bring Elba to life.

As our understanding of the various components broadened, the actual SoC architecture design activity then knew the details it needed in order finalize the design. We knew we had two Cortex-A9 macros, a Mali GPU and the various other components, but not too much about how we would best plug them together. Since we also wanted to investigate system level power management, many of the large system components were also placed into their own independent power domains. The layout of the design also became rather ...

Elba Processor Power Management

Having chosen the optimal implementation, as described in the previous blog, we now turned our attention to power management.

Simulations of Elba at this point of the program were starting to supply some rather noticeable power levels for the processor, especially at the design corner we were most familiar with. The worst case design corner is a statistical point across the variations that you could potentially see from a silicon process at a temperature that is assumed to not exist. Remember, ARM's primary market was mobile devices, so for these devices a manufacturer wanted to know that every chip delivered from the fab would achieve the defined performance. So speed would always be defined by the statistically slowest piece of silicon, and the power would be defined by the statistically fastest and hottest piece of silicon – neither of which would ever exist in reality, but allowed the manufacturer to maximise device yield without testing each part for its performance. You may know that around 1 billion phones were sold last year – and that would be a lot of cost to ‘speed-bin’ parts across that market.

There are various ways to speed-bin a SoC, but basically the two main o...

ARM DAC Review

The 48th DAC was held in San Diego this year and whenever DAC is not in Silicon Valley there is always a concern about how many people are going to show up. Fortunately the sun shone on San Diego and there seemed to be a good number of people in attendance.

This year, for only the second time in history, there was an ARM booth at DAC. In previous years we have shown demos within our partners’ booths but this year we had our own space as well as working with our partners as usual. One of the messages we were promoting at DAC the need for a complete system solution approach to design, as opposed a collection of components designed in isolation of each other. We call this Smarter Systems Solutions and John Heinlein gave a presentation on this subject on the Chip Estimate booth. During DAC, ARM also ...

"Wouldn't it be interesting if we..." - Giving Birth to 'Elba'

“Wouldn’t it be interesting if we....” That’s the way many step changes have started in ARM. In the next four blogs I’d like to take this opportunity to tell you about just one of those, we called it “The Elba Program”. The Elba program is just coming to its end, but its effect is starting to be seen in various places across the web as new markets and devices are starting to appear.

First, a very basic history lesson. ARM processors really took off as the processor that powered the first mobile phones. Phones as I’m sure you know need to be turned on to receive a call, and until more recently most calls were fairly short in comparison to the time a phone sat in what was called standby mode. This requirement quickly became the dominant characteristic for embedded processors and drove an entire branch of the semiconductor industry to look at manufacturing devices that consumed as little energy as possible when in standby at the cost of higher energy consumption when active. At the fabrication level, this technology gained a geometry label “LP” (low power), to differentiate it from the “G” (generic) process that was used by the more general purpose microprocessors.
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Upgrading Your Verification For Cache Coherency With Jasper!

Are you using a mobile device? Chances are you’re probably reading this blog post on one. You’re also probably reading this with the confidence that your device is doing what you intend it to do. As consumers, we place a lot of demands on not only our mobile devices but also the rest of our personal electronics. We want them to perform all sorts of tasks efficiently, accurately, and with minimal power consumption. As an engineer, you’re aware of the complex embedded SoC’s used in your device to make sure that it does what’s intended. Today’s embedded SoC’s are high performance, heterogeneous, and multi-processing systems.

In the future, most of these embedded SoC’s are likely to contain multiple caches that share a single memory resource. At a high level, cache coherency means that two caches cannot have same cache line in a dirty state and that if a cache contains a cache line in a unique state, that line must not be in another cache. In addition, at least one transaction must always be able make forward progress (no deadlock.) To prevent these cache coherency issues, ARM has included cache coherence extensions in their AMBA 4 protocol specification.

While this is a tremendou...

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