ARM Community: SoC Design - ARM Community

I hate reading manuals. Maybe it’s a guy thing or maybe it’s the engineer in me, but it’s pretty rare that I’ll bring home a shiny new device and then sit down and read the manual. Give me a few pictures or examples on how something should be used and I’m good to go. Not surprisingly, a lot of customers take this same approach with our software products. Immediately after installation they’ll start things up and look around for an examples directory long before they’ll ever click on the “Help” button.

This approach works well for a lot of tasks but when it comes to more complex tasks that example needs to be very sophisticated to be of value. System on chip (SoC) performance analysis, certainly meets that “complex task” threshold. The best way to analyze the performance of an SoC before it is built is by using a virtual prototype. Before any performance analysis work can be performed however, there is a long list of tasks to be performed. Models need to be assembled and configured for all of the important design elements, or even written if the models don’t already exist. These models need to be pulled together into a system configuration which matches the end design. Finally, software must be written to initialize all of the components in the system and then generate some meaningful traffic. Hopefully your virtual prototyping tool has some good data visualization tools. If not, you can add data extract...

Find out more about what ARM’s Processor Optimization Pack (POP) is and its advantages.

Like many people who work in high tech, from time to time I’ve had trouble explaining my profession to family and friends. Unless you are pretty tech savvy it is hard to understand exactly what a SoC engineer does everyday. The other day I was driving in my car dropping my son off at Cub Scouts when he asked me, “Dad what do you do at work?” It’s the kind of question that comes out of the blue and you struggle to answer. I paused for a few moments searching for a simplified answer and responded “I make ARM processors go faster.” He seemed satisfied with that answer, and quickly became distracted when his favorite song came on the radio; when you’re a seven year old you just love singing in the car!

When I joined ARM in 1997 I was a SoC engineer in ARM’s consulting group, the group’s main focus was to enable a Partner to get to market faster by taking advantage of AR...

At the TSMC Open Innovation Platform (OIP) forum in San Jose this week Mike Inglis, the General Manager of the Processor Division at ARM, presented a keynote speech succinctly titled “Enabling Smart System Design Through Collaboration, Optimization and Scalability”. This presentation outlined many of the challenges faced by silicon developers around the globe, and noted some solutions that can help reduce these design pains.

For me, the most important aspect of this talk was the public announcement of the availability of a new Cortex™-A5 Hard Macro for the TSMC 40nm Low Power node (40LP) which can achieve a whopping speed of over 1GHz in a tiny footprint of just 1mm2.

This Hard Macro is based on a uni-processor implementation of the Cortex-A5, and includes NEON™, Flo...

ARM IP and ARM processor usage is pervasive across multiple segments of the electronics industry. As shown in Figure 1, each of these market segments have unique design challenges and analysis drivers. For example, a SoC targeting a mobile handset or tablet will require high-performance, while still meeting the overall power budget. Memory and I/O IP on the other hand, must be designed for immunity to noise that is coupled via the power grid routing, the package, or the substrate. SoCs targeting automotive or medical industries must meet high reliability standards and minimize their electromagnetic interface (EMI) signature.


Using a power and noise budgeting methodology...

In the previous three blogs (Parts 1, 2 and 3) I’ve outlined the background and key decisions involved in the development and implementation of the Elba testchip. Now we’ll look at the final steps taken to bring Elba to life.

As our understanding of the various components broadened, the actual SoC architecture design activity then knew the details it needed in order finalize the design. We knew we had two Cortex-A9 macros, a Mali GPU and the various other components, but not too much about how we would best plug them together. Since we also wanted to investigate system level power management, many of the large system components were also placed into their own independent power domains. The layout of the design also became rather ...