ARM Community: SoC Design - ARM Community

In the world of the System on Chip (SoC) end users have come to expect a richer web experience, full HD video, full HD gaming and sophisticated applications leading to embedded processors becoming more powerful; wired and wireless communications becoming faster; and graphics and audio becoming more capable. As a result, the role of the interconnect that connects all these data producers and consumers together is becoming more demanding. To meet the increased demands, new protocols (AXI4TM,ACETM,ACE-LiteTM), new Corelink™NIC-400™ Interconnect, with new features such as Quality of Service(QoS-400TM), QoS Virtual Networks (QVN-400™), and Memory Management Units are being added to the interconnect. All of these have to be thoroughly understood to get the best performance out of your SoC.

A typical SoC (Figure 1) is constructed arou...

Power, performance and area or “PPA,” as it is called, has become a universally interesting topic to system-on-chip (SoC) designers around the world. Atrenta – an ARM Connected Community Partner and a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries – showcased a new and innovative design flow for early PPA estimation at last year’s ARM TechCon.

Design complexity now demands that all aspects of the design be co-optimized. If you reduce power, you will impact performance and area and so on. A holistic approach that balances all requirements of the chip is needed to deploy SoCs successfully.

Improving PPA by analyzing interconnect fabric earlier
Anyone will tell you that the interconnect...

Thank goodness for the new packetization, virtual networking and clock gating features of the ARM CoreLink NIC-400. I’m fed up with hearing about spurious comparisons between a single humungous crossbar switch and NoC solutions. No design of any complexity uses a single cross bar switch! Modern SoC designs integrate large numbers of IP cores supporting the de facto industry standard AMBA AXI interface (open to all) using a network of small switches to allow very high operating frequencies and reduced routing congestion while still maintaining very low latencies and simplicity and flexibility of design.

Smart customers evaluate the alternatives to compare performance (bandwidths and latencies) vs. cost in terms of silicon area, routing congestion, power and price.

Packetization is great to increase wire utilization, but comes with a packetization/depacketization overhead that costs latency, gates and power. So should be used where it helps most to cross long distances with multi-cycle timings, f...

In part 1 of this blog, I outlined the thought process behind the Elba program. Here I’ll look at the implementation decisions for the project.

In ARM there are various stages of maturity of a new processor development, reaching silicon implementation in various fabrication processes is one of those and it made sense to us that Elba must also be a full silicon implementation. In fact, just in case this does work, and what we think may happen does, we’ll implement the Cortex-A9 processor in a way such that ARM could commercialize and promote these “G” implementations as a new product. But what type of silicon? In ARM we often build silicon devices, but these typically are no more functional as a device than something that can execute a little code from on-chip memories. Great, so our goal to build a multi-GHz Cortex-A9 will be able to run Dhrystone – we need more than that . . . How much more? As it ended up, quite a bit more. ARM also develops the Mali 3D graphic processors, so the device should include the...