ARM Community: SoC Design - ARM Community

Power, performance and area or “PPA,” as it is called, has become a universally interesting topic to system-on-chip (SoC) designers around the world. Atrenta – an ARM Connected Community Partner and a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries – showcased a new and innovative design flow for early PPA estimation at last year’s ARM TechCon.

Design complexity now demands that all aspects of the design be co-optimized. If you reduce power, you will impact performance and area and so on. A holistic approach that balances all requirements of the chip is needed to deploy SoCs successfully.

Improving PPA by analyzing interconnect fabric earlier
Anyone will tell you that the interconnect...

今天，ARM Cortex-A7 的隆重推出…标志着 big.Little 处理架构的最终实现！

我驾驶着一辆节能型的本田飞度行驶在 20 英里的市区上班途中。有时我会突发奇想，希望在自己的座驾上安装一个更快的引擎，但大部分时间我还是对自己驾驶的节能车辆感到很满意。但我必须承认我曾抗拒换一辆经济型轿车；我时常梦想自己拥有像保时捷或宝马车那样的性能，但只希望在驾车的小部分时间里拥有这种卓越的性能。如果我能驾驶一辆平均能效保持在四缸引擎范围内，而在需要最高性能的片刻可迅速切换到高性能的涡轮增压式 V8 引擎汽车，那该有多好啊？如果平均燃油能效接近于 4 缸引擎，而最高性能接近于涡轮增压式 V8 引擎的性能，会怎样？
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ARM Cortex-A7 processor…It's all about right-sized equipment.
In Part 1 of this blog we saw how right-sizing of air conditioning is vitally important because it performs three different functions simultaneously: Cooling, dehumidification and ventilation. Increases in efficiency could be obtained by separating out these three functions and optimizing them independently. As we saw last time, pumping air through ducts is inefficient due to the wasted pumping energy. You could use a hydronic system like a traditional underfloor heating system as is common in northern Europe, but with cooling in the ceiling as well as heating in the floor. Pumping water is a more efficient way to move energy than air. Even though the water pipe is physically smaller than an air duct, in terms of thermal energy transfer capacity it's a fatter pipe. But this wouldn't dehumidify or ventilate, so you'd still need a very small A/C system with air ducts to provide these functions. Duct size and pumping losses would be much lower than a pure ducted central air system though...

Thank goodness for the new packetization, virtual networking and clock gating features of the ARM CoreLink NIC-400. I’m fed up with hearing about spurious comparisons between a single humungous crossbar switch and NoC solutions. No design of any complexity uses a single cross bar switch! Modern SoC designs integrate large numbers of IP cores supporting the de facto industry standard AMBA AXI interface (open to all) using a network of small switches to allow very high operating frequencies and reduced routing congestion while still maintaining very low latencies and simplicity and flexibility of design.

Smart customers evaluate the alternatives to compare performance (bandwidths and latencies) vs. cost in terms of silicon area, routing congestion, power and price.

Packetization is great to increase wire utilization, but comes with a packetization/depacketization overhead that costs latency, gates and power. So should be used where it helps most to cross long distances with multi-cycle timings, f...

Are you using a mobile device? Chances are you’re probably reading this blog post on one. You’re also probably reading this with the confidence that your device is doing what you intend it to do. As consumers, we place a lot of demands on not only our mobile devices but also the rest of our personal electronics. We want them to perform all sorts of tasks efficiently, accurately, and with minimal power consumption. As an engineer, you’re aware of the complex embedded SoC’s used in your device to make sure that it does what’s intended. Today’s embedded SoC’s are high performance, heterogeneous, and multi-processing systems.

In the future, most of these embedded SoC’s are likely to contain multiple caches that share a single memory resource. At a high level, cache coherency means that two caches cannot have same cache line in a dirty state and that if a cache contains a cache line in a unique state, that line must not be in another cache. In addition, at least one transaction must always be able make forward progress (no deadlock.) To prevent these cache coherency issues, ARM has included cache coherence extensions in their AMBA 4 protocol specification.

While this is a tremendou...