ARM Community: SoC Design - ARM Community

If you missed DAC, then you missed the seminar on cache coherency and verification of cache coherency given by ARM and Jasper. Learn how to overcome the typical challenges of capturing the intent, reviewing possible scenarios and how to correct errors in functional terms as they relate to the specification.

The seminar (on-line recording) kicked off with a discussion on how the implementation of hardware-based coherency in high-performance parallel compute environments is not new. The seminar quickly revealed that architects and designers of high-performance, heterogeneous, embedded multi-processing SoC’s, particularly those with one or more caches and when many masters share a single area of memory, now require robust specifications, design & verification tools and systems IP, to ensure their devices minimize off-chip memory transactions, while maximizing performance and power efficiency. The seminar then went on to explain why ARM has chosen to include Coherency Extensions...

High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM’s big.LITTLE processing. In case you missed the announcements, the big.LITTLE technology offers an innovative way to run the ‘always on’ tasks on the highly efficient Cortex™-A7 processor, while the high performance and responsive applications are predominantly executed on the Cortex™-A15 processor. So what does this have to do with AMBA 4? Well AMBA 4 ACE and the CoreLink™ CCI-400 Cache Coherent Interconnect offer the critical glue to join these processors together into a big.LITTLE multi-processing (MP) system. Let me explain…

Earlier this year ARM announced the public release of the AMBA 4 phase 2 specification including AC...