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ARM Community: SoC Design - ARM Community

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An Advanced Timing Sign-off Methodology for the SoC Design Ecosystem

The System-on-a-Chip (SoC) ecosystem spans the gamut of designs from high-end servers to low-power mobile consumer segments. A large and heterogeneous set of players (foundries, IP vendors, SoC integrators, etc.) has a stake in fostering the success of the ecosystem model. While the integrated device manufacturer (IDM) model has undeniable value in terms of bringing to bear large resources in tackling technology barriers, one could argue that the rapid-fire smartphone revolution we have experienced in the last five years owes in large part to the broad-based innovation enabled by the SoC ecosystem model. This blog examines how the changing dynamics of SoCs are driving changes in verification requirements, tools and flows and thereby changing the timing sign-off paradigm.

ARM should be applauded for the significant role it has played in bootstrapping and further enabling the SoC ecosystem model. By licensing its processor and digital IP instead of manufacturing its own chips, ARM has freed its partners to aggressively build and refine their products without being reliant on general purpose devices or rigid form factors. And it did not hurt that ARM’s advantage in the ...

The World of ARM Multicore Explained

Unlike many it seems, having now returned from New Zealand (where I went to attend Multicore World - read about it HERE), I don’t have that strong desire to emigrate. Not that there was anything wrong with New Zealand, just the opposite: it’s a lovely country and despite its small population, I found it to hold a surprisingly international feel and active technical community.

As the 2nd year of Multicore World starts to take shape, I thought it may be interesting for those that didn’t find themselves just passing to catch a few of last year’s talks. In my talk, I offered a view across ARM multicore technology from its first roots through to big.LITTLE™ and the future of Accelerated Compute. Want to know a little about why multicore in ARM looks the way it does? Catch the video HERE.
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Breathing New Life into the Foundry-Fabless Business Model

Early last week, GLOBALFOUNDRIES jointly announced with ARM another important milestone in our longstanding collaboration to deliver optimized SoC solutions for ARM® processor designs on GLOBALFOUNDRIES’ leading-edge process technology. We’re extending the agreement to include our 20nm planar offering, next-generation 3D FinFET transistor technology, and ARM’s Mali™ GPUs.

Our collaboration with ARM goes back many years, and its evolution parallels some of the critical developments in the larger semiconductor industry during the same timeframe. We began this work back when the 65nm node was the bleeding edge and our biggest concern was the integration of strained silicon to boost electron mobility. (Those were the days!) Of course today we face a daunting list of new challenges ranging from multiple patterning and EUV lithography to new device architectures such as high-k metal gate (HKMG) and FinFET. But the goal remains essentially the s...

How do you take an ARM POP up one more notch?

ARM announced its performance-boosting POPTM IP for the ARM® CortexTM-A9 processor in late 2010. The ARM Cortex-A9 POP technology combines optimized ARM Artisan® logic, memory, and physical IP with ARM implementation knowledge and engineering to help SoC design teams get the most out of any process technology in terms of power, performance, and area (PPA). Using the benchmark report included in the POP technology, any SoC design team can obtain superior PPA results when hardening an ARM Cortex-A9 processor and they’ll achieve desired results faster. ARM now offers several POP solutions for the ARM Cortex-A15, Cortex-A9, and ...

Configure AMBA Fast With Early Power, Performance & Area Tools

Back in April, I wrote about how Atrenta – an ARM Connected Community Partner – was helping to tame the SoC design problem with early power, performance and area or ePPA technology. ePPA holds great promise to help SoC designers hone in on the optimal architecture vey early in the design process – well before detailed implementation begins.

Juggling power, performance and area requirements for an advanced SoC is a daunting task. A critical component in the design equation is the on-chip interconnect. With that in mind, we went to the Design Automation Conference in San Francisco this past June to explain our ePPA strategy to attendees.

We participated in the ARM Connected Community Pavilion at the show, and demonstrated how to take various configurations of ...
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