ARM Community: A DATE with Computing Destiny - ARM Community

I’m all set for my keynote at this year’s Design Automation & Test in Europe Conference (DATE), March 18-22, 2013, Grenoble, France. It will be a pleasure to return to one of the industry’s most stimulating events and to make what I believe will be an exciting contribution to the debate on Energy Efficiency.

One of the ‘Special Days’ at this year’s conference will focus on ‘High-Performance Low-Power Computing’ on March 20, an area that is bringing new challenges to the system design community. This Special Day will feature four sessions covering System approaches, IC Architecture approaches, Many-Core SoC approaches and Fabrication Technology approaches for Energy-Efficiency. I have been invited to deliver the keynote on Energy-Efficient Computing at 1:30pm.

I’m fortunate that my work at ARM and our heritage in low power, high performance – particularly in the mobile space, enables me to speak with a pretty long view of this subject.

Since the very first mobile computer, power efficiency has been a key measure for success. In today’s hyper-connected world, our need for performance is ever increasing, and the energy cost of performance has risen well beyond just the life of the battery in mobile devices. Energy efficiency is now the key driver across most consumer and enterprise products and has become the primary limit in the delivery of high performance. During my keynote I will consider the various power related limitations of compute while discovering how the techniques and new capabilities introduced into mobile computing also bring the flexibility to address the limitations of the traditional computing approach.

We can think of three key phases in this journey: (1) Phase One began in the 1990’s with single core designs, such as the ARM1176 CPU paired with a DSP such as the + TI C64x. (2) Phase Two saw the Multi-core cluster based designs like the ARM11 MPCore and the ARM Cortex^TM-A9 MPCore often used with specialist accelerators. (3) Phase Three is where we are now: Multi-cluster designs such as ARM big.LITTLE^TM processing technology with Cortex-A15 and Cortex-A7 processors and ARM Mali^TM GP-GPU graphic acceleration. Big.LITTLE technology ensures application tasks are using the right processor for the right job, to produce 70% energy savings on common workloads.

What could become (4) Phase Four is where we are potentially heading: ‘Scalable Compute Units’ – a future towards which ARM has already laid the required IP tracks. This introduces a new way of understanding, and also driving energy efficiency, while supporting the software paradigms and models familiar to the software community.

To begin, we need to abstract the thought of building systems with single discrete CPUs and start thinking about ‘Units of Compute,’ each unit managed by one of today’s SMP operating system, operating within an partitioned coherent region of the globally shared memory map. It is then a question of how to use these compute units in a SoC and scale them into many-core systems. The size and capability of any specific compute unit is defined by the target market’s ability to utilize the SMP resources the unit defines, ranging from a single CPU core up to a multi-core, multi-cluster design with arrays of GP-GPU compute. Today such units can be constructed from a single Cortex-A5, through big.LITTLE with GP-GPU acceleration, to a 16-way Cortex-A57.

From this concept we consider the benefit from a common global address space across the whole system with a very scalable global cached communication path between compute nodes isolated from traditional bottlenecks to DDR & IO.

As the SMP operating system (OS) won’t scale as far as the hardware can, we can then consider how any access to remote regions could still provide coherent shared memory between compute units while keeping the central part of the OS tied to each compute unit’s local coherent region

Because of advances such as big.LITTLE processing we can now begin to view the CPU as no longer having a single pipeline, and think of it more in the domain of a single SMP OS’s ownership. This thinking will start to include other API abstracted processors and accelerators, such as ARM Mali GP-GPU through the architecture currently being defined with in the HSA consortium. As the complex of such compute sub-systems has increased, ARM has used this basis to develop what can now be viewed as Compute Units from a single CPUs through to multiple clusters of multi-core CPUs utilizing MPCore technology, with the system IP such as CoreLink^TM Cache Coherent technology (CCI-400, CCN-504) being used within the Compute Unit to scale the overall capability of the design.

ARM has also recently introduced the Cortex-A50 series of ARMv8 CPUs, extending the concept of the Compute Node to 64-bits which through the capabilities it enables through a common global address, enables the development of a unified architecture with which to build many-core systems from multiple compute units and as such to nurture the future of the ARM ecosystem.

These and other developments will continue to steer us towards the low power, high performance course that government, business and consumers all need to take for a sustainable and dynamic future.

John Goodacre, Director of Technology and Systems, ARM. John joined ARM in February 2002 and took responsibility for their platform architecture. Today he is Director of Program Management focused on various programs around the application processor’s technology roadmap including the definition and market development of the ARM MPCore multicore processor technology.

Prior to working at ARM, he specialized in enterprise software having worked for Microsoft for 5 years, firstly as Group Program Manager in the Exchange Server group and latterly as the manager of a team developing mobile phones software.

Graduating from the University of York with a BSc in Computer Science, John has over 20 years experience of realizing new technologies in the engineering industry.