ARM Community: Implementing ARM Cortex-A7 in a 14nm Samsung FinFET Process - ARM Community

Recently, ARM, Samsung and Cadence announced a joint tapeout of an ARM Cortex^TM-A7 based test chip on Samsung’s 14nm FinFET process.

This collaboration is significant due to a couple of reasons as detailed in this blog and video below:



14nm/FinFET technology
The importance of FinFETs as the next evolution in process technology was resoundingly validated at ARM TechCon last year, where many of the papers touted improvements in the power/performance curve with the usage of FinFETs. Essentially, designers can get better performance with the same power profile, or lower power with the same performance. A 14nm FinFET process can potentially offer a 40-50% performance increase or a 50% power reduction compared to a 28nm process. With power density threatening to become a roadblock to future system on chip (SoC) innovation, FinFET technology is very welcome news indeed.

However, applying a new process technology such as 14nm/FinFETs still requires much effort. The process technology has to mature, EDA methodologies have to be established, and libraries and IP have to be developed. The test chip tapeout referred to above includes a 14nm/FinFET Cortex-A7 along with ARM 14nm/FinFET libraries and a Samsung 14nm SRAM. It was implemented with Cadence’s 14nm methodology during an 8-week period. The tapeout is an important milestone that shows progress in the industry’s move towards being able to mass produce 14nm/FinFET SoCs.

The ARM Cortex-A7
The ARM Cortex-A7 processor is starting to go mainstream in new high-end smartphone applications. Today, the ARM Cortex-A7 is used as the “LITTLE” part in ARM’s big.LITTLE configuration along with the ARM Cortex-A15, offloading computing tasks and improving energy efficiency and battery life.

In addition, it’s also being targeted as the main processor core in new entry level and mid-range smartphones, significantly improving power, performance and area of those devices that used a previous generation core. For applications that don’t need the peak computing power of a Cortex-A15 or Cortex-A9 processor, the Cortex-A7 alternative offers reasonably good performance at significantly lower power and area.

14nm/FinFET technology can potentially amplify the advantage of ARM Cortex-A7 processors by further improving the Cortex-A7’s power/performance benefits.

The entire tapeout project was completed within a tightly-packed schedule of 8 weeks. During that time, engineers from Samsung, ARM and Cadence located in multiple locations around the globe (Korea, Taiwan, U.K., Germany and the U.S.) worked together diligently to make this tapeout successful. As a side note, the tapeout also demonstrates the realities of today’s large design teams, where designers must interact with others in different locations and time zones.

The Methodology Used
As mentioned earlier, the Cadence 14nm methodology was used for this tapeout. This included the following:

• Virtuoso 6.1.5 and Advanced Node environment were used for the standard cell design
• RTL Compiler, Encounter Digital Implementation System (EDI System) and NanoRoutewere used for synthesis and place-and-route respectively
• QRC, Encounter Timing System (ETS), and Encounter Power System (EPS) were used for extraction, as well as timing and power signoff.

From a user perspective, a 14nm/FinFET design methodology is similar to 20nm. Double-patterning is required at 14nm, just like 20nm. Under the hood, EDI System and NanoRoute handle 14nm/FinFET design rules automatically, including same-mask metal rules to prevent double patterning conflicts. The use models for QRC, ETS and EPS signoff at 14nm are also similar to that of 20nm. However, to ensure correct handling of the 14nm/FinFET design rules, as well as making sure the new libraries could be used efficiently, R&D teams from all three companies had to work closely together.

In short, the tapeout of ARM’s Cortex-A7 on Samsung’s 14nm/FinFET process is a significant milestone towards 14nm readiness. We’re all expecting to see more partnership work to come to fruition too, bridging the gap between early testing and production. For more information, see the feature story at Cadence.com. In addition, visit the ARM, Cadence and Samsung booths at the Common Platform Forum in Santa Clara, CA. Dispesh Patel, EVP and General Manager - PIPD, PIEX, ARM also will discuss this collaboration further in his keynote.

Guest Blogger:

Wei Lii Tan, Sr. Product Marketing Manager, Cadence Design Systems, responsible for Encounter digital implementation products. He holds a bachelor’s and master’s degree in electrical engineering from Mississippi State University, as well as an M.B.A. from Santa Clara University. Wei Lii has 10 years experience in application engineering and product management roles in the EDA industry.

ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.

The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.