ARM Community: Low Power and its Future? - ARM Community

Five years ago, ARM R&D Fellows Robert Aitken and David Flynn presented several low-power design and implementation techniques which were discussed in detail in their book (co-authored by Michael Keating, Alan Gibbons and Kaijian Shi from Synopsys) titled “Low Power Methodology Manual – For System-on-Chip Design.” This manual has been well appreciated by the industry. Anil Mankar, Sr. VP and Chief Development Officer from Conexant Systems remarked, “The LPMM (Low Power Methodology Manual) enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SoC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.”

Fast forward five years. In today’s high performance and low power chip designs, we seem to be using in automated flows almost all of the low-power techniques discussed: clock gating, power gating, multi-Vt, multi-VDD and adaptive scaling in the form of dynamic voltage and frequency scaling (DVFS) or adaptive voltage scaling (AVS). The LPMM also discusses the importance of selecting physical IP to support the goals, specifically the low-power goals, of a given design. Just as low-power techniques are evolving, so too is the physical IP used to implement these techniques.

Several recent announcements highlight the ARM commitment to emerging technology; a great example of which is the popular FinFET. An announcement on the ARM-TSMC collaboration for FinFETs can be read here. And the press release discussing the GLOBALFOUNDRIES-ARM collaboration for FinFETS can be read here.


We should really give a big thanks to FinFETs as they provide higher mobility, reduced body effect, and reduced device capacitance. This enables both high performance and lower power. The improved Ion/Ioff ratio makes the FinFET a more efficient switch. Isn’t that great? It will be very interesting to see how these well-proven, low-power design techniques such as DVFS are deployed when we move down to 16nm and below with FinFETs.

Low power has been embedded in the ARM DNA since the beginning. The original ARM mission statement integrated designing for low power and high performance. Over twenty years later, the ARM processors and architectures have proven to be highly tuned for low power while still achieving high performance. The same low power DNA is engrained in all of the ARM Artisan Physical IP products. Artisan Physical IP offers low-power IP while maintaining high performance. Standard cells/logic libraries, SRAM memories, register files, and POP^TM IP all have one thing in common: low power. Although power optimizations have to be addressed at different levels such as system, architecture, RTL, chip and block levels, ARM’s view on low power is that it must start at physical IP level. Physical IP is designed for particular process utilizing available Vt options. The ARM Power Management Kit (PMK) along with ARM multi-channel libraries provide process and Vt choices to help designers optimize power not only at the block level, but also at the chip and system level.


I recently had the opportunity to present “Low Power Design with ARM Physical IP and POP IP” at a low-power technology summit event, hosted by Cadence. It was a packed auditorium with an audience of approximately 200 designers, technical managers and architects of Low Power SoCs. The day started off with a visionary key note speech from the low power “rock star” Dr. Jan Rabaey from the University of California at Berkeley. The following are some of my key takeaways from this event and these techniques are certainly going to buck the trends for the future of low power. Continued voltage scaling (because power is proportional to CV²); self-adaptation (self-timed circuits); “razorized pipeline”; statistical, or non-deterministic, computing (this sounds like some “random” fun); emerging devices (nanowires and of course FinFETs); NEMS (nanoelectromechanical systems) and energy proportional systems (for example thermal monitors, PVT sensors, leakage sensors and even aging sensors!). These very advanced low-power techniques look so promising that an overall energy reduction of 10X could very well be achieved. As chip designers and system architects, we seem to be leaving performance and power on the table because we tend to over-margin in designing for worst case scenarios. Eliminating margins will result in zero margins and even “negative margins.” This is where analog design techniques have to be incorporated into digital implementations to save power and thereby keep the globe green!


On a lighter side there were also some very interesting facts about our own human brain. Did you know that an average power consumed by a human brain is about 20 Watts!? This is roughly about 15 milliWatts/cm³ with a storage capacity of 100K TeraByte. I wonder how many CPUs and storage devices you need to build such a massively parallel and statistical computing machine (aka our own brain!) with a nearly unlimited storage capacity.

So you might wonder, what’s next? Gone are the days where you design a digital chip for one PVT corner and for a worst-case scenario. Think about a chip where you can seamlessly control variations, change voltage, temperature and frequency with ease, saving a ton of power by going in and out of several different power-down or leakage-saving modes. Making use of analog techniques to lower power in digital circuits is truly a way forward, and the future looks even brighter and greener.

With so many positive developments, I wonder what the next five years will bring.

Sathyanath (Sathya) Subramanian, Technical Marketing Manager, ARM, is responsible for technical marketing for POP Products and is part of ARM’s Physical IP Division. Sathya recently joined ARM, bringing more than 15 years of high-performance/low-power ASIC/SOC design and implementation experience. He holds MSEE and MBA.