ARM Community: 20nm Tapeout with ARM Cortex-M0 - The Inside Story - ARM Community

A few months ago, ARM’s new Hsinchu Design Center taped out a 20nm ARM Cortex™-M0 test chip using a mostly Cadence tool flow. All early 20nm tapeouts are learning experiences, and this one was no exception. Here’s an inside look at the challenges that were encountered and the lessons that were learned.

First, here’s some information about the test chip. It includes the Cortex-M0 microcontroller, which is the one of the smallest, lowest power, and most energy-efficient ARM processors available (further information about the Cortex-M0 is available at the ARM web site). It also contains 16 Kbytes RAM, a PLL, and some simple peripherals including an interrupt controller. The clock speed is around 200 MHz and the chip contains approximately 61K instances (approximately 200k transistors). The test chip uses the TSMC 20SOC process.

The test chip was the first project for the new ARM design center located in Hsinchu, Taiwan. According to Tim Whitfield, director of engineering for the center, part of the design center’s charter is to serve as a “conduit” between ARM’s physical IP and processor divisions, EDA providers, and wafer process developers to ensure that the ecosystem for advanced-node ICs is working well. Indeed, Whitfield said, the primary goal of the test chip was “to provide feedback to our physical IP team on the optimizations, ease-of-use and quality of their Alpha standard cells and SRAM products.”

To design the chip, ARM engineers used a Cadence digital implementation flow including RTL Compiler, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, and QRC Extraction. They used the Mentor Graphics Calibre tool for final DRC signoff. “We found that the [Cadence] flow is quite ready, more ready than we originally thought,” said Frank Chen, who leads the Taiwan AE team for Cadence. “Originally, we thought we would run into a lot of 20nm-related problems in routing or timing or double patterning, and most of them didn’t happen, except we did have some routing rule problems.”

DRC and Routing Challenges

As Whitfield noted, the design did not target aggressive PPA (power, performance, area) goals, but designers still ran into a few challenges. The key challenge was to understand the implications of the complex 20nm design rules on the tools and design flows. Designers analyzed power distribution, pin access and placement density, and how they impact SoC routability. This information was provided back to the physical IP group for further refinement of physical IP architecture and optimizations. Designers also had to cope with the inevitable issues resulting from early versions of process design rules, physical IP, and tooling, causing continual changes in the implementation methodology and flow.

Whitfield said that most of the challenges were around routability and the need to understand local density. “There are some very different things going on at 20nm that you have to be aware of,” he said. “It is important to work closely with the [standard cell] library designers to understand the expected power distribution network. This has to be carefully designed to ensure the critical local routing resource is not blocked.” With complex standard cells, he noted, local routing can be very difficult. “Working out how you pad those cells, or how you get the routes to reference the pins in the right way, is really quite critical,” he said.

Double patterning, which was used on two layers of the test chip, also raised some DRC challenges. On the plus side, “once we got the [Cadence] tool set up correctly, the tool was actually very good,” Whitfield said. From a tool standpoint, Chen noted, “originally we thought double patterning would be one of the challenges, but it turned out to be okay.”

It’s a Different Node

What was learned from this test chip experience? Given the challenges of place and route with double patterning technology, Whitfield said, “You’ve got to understand that there are some significant differences between other technology generations and 20nm.” These challenges include density, complexity, power distribution, and a cost/benefit decision on how many double patterning layers to use. Those layers are costly, but they are also essential for achieving the benefits of scaling that the 20nm node promises. And that’s why routing density is so important with double patterning – you want to get your money’s worth on those expensive layers, and use as few as possible.

The point of this early collaboration between ARM and Cadence is to make life easier for designers when full 20nm production begins. When 20nm goes mainstream, Whitfield said, “We want to have the knowledge in house and the ecosystem in place to support our partners, so they don’t have to go through the same learning experience. We want to get an early view of what the problems might be in a real SoC when people are using our logical and physical IP.”


Guest Partner Blogger:

Richard Goering started writing about EDA in 1985, when he was working for Computer Design magazine. He was the EE Times EDA editor for 17 years. He is currently senior manager of technical communications at Cadence, where he authors the Industry Insights blog.

ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.

The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.