A typical SoC (Figure 1) is constructed around a cascade of interconnects, with each interconnect being a configuration of an interconnect design IP (CoreLinkTM Network Interconnect NIC-301TM, NIC-400TM, and CoreLinkTMCCI-400TM Cache Coherent Interconnect) and each interconnect design IP having a huge number of configuration and programming options.
When building such an SoC, it is important to ensure that the SoC Interconnect is functionally correct and that it supports the latency and bandwidth requirements of the intended application use cases. This can be very challenging, as it requires the creation of a testbench for the specific use of verifying the interconnect and measuring performance, or waiting until the full SoC is implemented and running on an emulation platform (which is very late in the design cycle).
The need for cycle accurate, early design cycle performance analysis and verification of SoC Interconnects led to the development of the Cadence Interconnect Workbench.
Cadence Interconnect Workbench
So, how does the Interconnect Workbench (Figure 2) help you do early design cycle performance analysis and verification of SoC interconnects? The answer is automation!
Starting with the IP-XACT description of the interconnect RTL, Interconnect Workbench generates a UVM e or UVM SystemVerilog testbench that configures all the Verification IP required to provide stimulus and responses to the interconnect. There are 2 flavors of the testbench – one tailored to the goal of verification, and one tailored to the goal of performance analysis(which adds Performance Generators and a Performance Monitor to the testbench). As you can imagine, this capability alone can remove weeks from a project schedule.
Once the testbench is generated the next step is to simulate, either interactively for debug or in a regression for analysis later. Again, Interconnect Workbench helps here by generating the infrastructure required to run the simulations on Cadence®Incisive® Enterprise Simulator, and can also use Cadence®Incisive® Enterprise Manager for regression management.
The final step in the process is analysis. Performance analysis is done using the Interconnect Workbench Performance Analyzer (Figure 3) which adds the ability to graphically analyze, review and interpret the performance metrics gathered during a performance regression. Verification analysis(Figure 4) is done via Cadence Incisive vManager; the Verification Plan (vPlan)that Interconnect Workbench generates gives a good starting point for MetricDriven Verification (MDV).
To see the Interconnect Workbench in action, please take a look at the videobelow that was recorded at DAC2012 in San Francisco.
If you’re interested in additional information please contact: Stewart Penman(firstname.lastname@example.org),Nick Heaton(email@example.com) ,Steve Brown(firstname.lastname@example.org)
ARM Partner Blogger:
Stewart currently works in the Cadence Research & Development organization as a developer of the Cadence Interconnect Workbench solutions.
ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.
The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.
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