ARM Community: How do you take an ARM POP up one more notch? - ARM Community

ARM announced its performance-boosting POP^TM IP for the ARM® Cortex^TM-A9 processor in late 2010. The ARM Cortex-A9 POP technology combines optimized ARM Artisan® logic, memory, and physical IP with ARM implementation knowledge and engineering to help SoC design teams get the most out of any process technology in terms of power, performance, and area (PPA). Using the benchmark report included in the POP technology, any SoC design team can obtain superior PPA results when hardening an ARM Cortex-A9 processor and they’ll achieve desired results faster. ARM now offers several POP solutions for the ARM Cortex-A15, Cortex-A9, and Cortex-A7 processors and ARM customers have already achieved processor clock speeds in excess of 1GHz—sometimes considerably more than 1GHz—using the appropriate ARM POP packages while targeting TSMC 40nm G and LP and 32nm LP process technologies. The resulting solution is available for license from ARM to accelerate the implementation of ARM processors.

Now, Cadence has teamed with ARM to take those results to yet another level through the incorporation of Cadence-specific digital implementation knowledge combined with a process-specific design flow that employs several Cadence EDA tools. The first target processor for this technology partnership is the ARM Cortex-A9 processor and the target process technology for this partnership is the TSMC CLN40LP process. The result is a significant PPA improvement as well as a reduction in the amount of time needed to tape out an IC design.

The integrated Cadence tool flow involved in this ARM POP-optimized flow includes many components of the Cadence Encounter RTL-to-GDSII technology including two key ones: the Cadence RTL Compiler-Physical and Cadence CCOpt (clock-concurrent optimization). Using a set of POP-specific scripts developed for these tools, this flow can produce optimal, hardened cores for a targeted process technology. The full tool flow includes:

• Physical-aware synthesis
• Scan insertion
• Floorplanning and power grid creation
• Placement and placement-aware scan reordering
• CCOpt clock tree synthesis and optimization
• Placement
• Signal-integrity-aware routing
• Extraction across multiple RC corners
• Leakage optimization

The result of this process-optimized flow is a significant improvement in clock speed and a significant reduction in power consumption.

Of all the steps in this POP-optimized flow, the one that might be least familiar to you is CCOpt, a relatively recent addition to the Cadence Encounter Digital Implementation tool flow. In the conventional approach most used today, synthesis, floorplanning, initial placement, and physical optimization occur in the realm of an “ideal clock.” Ideal clock edges arrive at every flip-flop in an IP block and on the entire SoC design at precisely the same moment. There is no clock skew anywhere on a chip in this idealized world. Clock tree synthesis then attempts to make this assumption true by building a clock tree that delivers “ideal clocks” as closely as possible through schemes designed to equalize clock skew across the entire IP block or the chip.

As clock frequencies climb, this feat becomes harder and harder. CCOpt replaces skew-driven clock-tree synthesis with a physically driven clock-tree optimizer that balances clock and logic delays. This unique approach speeds timing closure, boosts clock speeds, reduces area, and cuts power consumption—the “superfecta” of clock tree synthesis. CCOpt alone has been able to produce these kinds of results for high-speed processor designs:

• Clock tree power reduction up to 30% and total power reduction up to 10%
• Clock-rate improvements up to 100 MHz for a design running in the GHz range
• Clock tree area reduction up to 30%

(For more information on the CCOpt tool, see “Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?” by Steve Leibson and “Why Cadence Bought Azuro – A Closer Look” by Richard Goering)

Although the result of this first POP collaboration between ARM and Cadence targets the ARM Cortex-A9 processor in a specific TSMC 40nm process technology, this announcement is a great beginning for combined solutions consisting of ARM POP IP tightly coupled to the Cadence Encounter Digital Platform. Stay tuned for further developments in this direction.

Partner Blogger:

Steve Leibson, Marketing Director, Cadence, Long ago in a far-away galaxy called Colorado, Steve Leibson designed computers and workstations. Then he crossed over (see “Something, Something, Something Dark Side”) and became a journalist for the electronics industry at EDN Magazine and then Microprocessor Report. He’s currently working on his third career as a Marketing Director at Cadence Design Systems in Silicon Valley. See his daily commentary on IC, board, and system design in the EDA360 Insider and the Denali Memory Report.

ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.

The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.