Let’s put the tabloid down and look at the facts from a few different perspectives.
TSMC is building its next GIGAFAB™ in Central Taiwan to and augmenting its existing 300mm facilities in the north and south. GLOBALFOUNDRIES is bringing its new fab in Saratoga County, New York online right now. Recently Samsung completed an investment of $3.6B in its Austin, Texas facility and is reportedly constructing a new fab in Korea in support of its growing foundry business. There has been consolidation at the leading edge, but there is no shortage of capital going into this market to assure capacity growth well into the future. Total foundry capex in 2011 was $16 billion compared to $10.7 billion by Intel, the top integrated fab player. 2012 investment is projected to be even stronger at around $17 billion. That’s a pretty healthy investment for an industry allegedly on the ropes.
IP Ecosystem. The IP ecosystem in support of these advanced technology manufacturing processes continues to strengthen and grow. This ecosystem is diverse and vibrant, with today’s IP providers offering a many IP types, spanning a wide range of power, performance and area tradeoffs. As an example, at 45 and 40nm various industry databases list between 450-620 licensable IP blocks available. Furthermore, the latest IP developments at 45nm and 28nm include extensive power management capabilities, cost tradeoffs and implementation options that give designers choices for their chip. Only through this ecosystem diversity can we have the rich and competitive landscape to address the many market segments the industry serves. If you are like me, you appreciate the continued improvement in value for your electronics dollar that this ecosystem and the fabless model enable.
Technology Development. Major technology investments are occurring across the foundry space, with new leading-edge R&D investments in fundamental process technology being made. These investments span major companies like IBM, TSMC, Samsung, GLOBALFOUNDRIES, research consortia like IMEC and even new entrants like Suvolta, all of which are driving for aggressive technologies. Today, 32 and 28nm products are in production and many more ramping to production. Following that, there is a range of solutions already announced at 20nm that deliver the next node of planar bulk CMOS scaling. Furthermore, the industry has clearly shown its commitment to investing in the next wave of 20nm and 14nm solutions beyond bulk ranging from FinFET to fully depleted SOI. I recently attended the GSA Silicon Summit where leaders across the industry discussed not one but many possible solutions to assure scaling well into the future. And while there is lots of focus in the media about the early FinFETs in production today, like any new technology, the initial offering is narrowly targeted and not broadly suited for the kinds of diverse SoC design decisions that make our industry broadly viable. The foundry and IP business model is integral to bringing those leading-edge technologies to a wider range of designers.
It’s true that advanced technology transitions do sometimes have slow spots along the way. Today, the important shift from PolySiON (Polysilicon oxynitride) to HKMG (High-K metal gate) dielectrics is taking some time to get right but it delivers significant gate leakage benefits. This is nothing new: think back to the first rollout of copper interconnect metallization. The difficulty in achieving reliable copper processing, CMP planarization and problems like via pullback caused a significant delay during that similarly important industry transition around 90nm. But copper has major advantages and every leading-edge process is in production with copper metallization today. Do you hear of any problems with copper now? These transition problems, while not to be minimized, are mere blips on the radar that do not reflect the incredible diversity, innovation, and resiliency that our semiconductor industry has produced.
I spend a lot of my time monitoring these industry trends and am excited at what is in front of the industry. I, for one, will not be writing an obituary to the foundry and IP business model anytime soon.
I welcome your thoughts and comments, and you can follow me on this blog forum as I share more thoughts about IP in the coming months.
John Heinlein, Ph.D. is Vice President of Marketing, Physical IP Division, ARM, where he is responsible for directing both the Physical IP roadmap and engagements with key strategic customers. John has worked extensively with semiconductor leaders worldwide for many years, with a special focus on Asia. In his current role his goal is to drive adoption of ARM Physical IP across the SOC design community. Prior to joining ARM, John was with Transmeta Corporation for nearly 11 years.He holds a Ph.D. and M.S. in Electrical Engineering from Stanford University, and a B.S. in Computer Engineering from Carnegie Mellon University. John is an avid snowboarder and triathlete and former scuba diving instructor (he once swam with a whale shark!).
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