Fast forward to present day. Now, we have the latest smartphones – mobile computing platforms featuring a PDA, camera, GPS, WiFi, web browser, touchscreen and of course, cell phone. The typical advanced smartphone is based on the ARM® CortexTM-A9 processor core on 45nm to 28nm process technologies, running at or greater than 1GHz with limited battery life of approximately 10 hours max.
Whoa …..so what happened to the battery life?? Granted there are phenomenally greater features and performance, at the cost of power, i.e. 40x in performance from the Newton but one-third of the usage (talk time or web-browsing). The user experience is cut short due to battery life.
So how do you design a device today that offers the best of both worlds?
SoC designers have applied various low-power design methodologies and techniques to reduce power consumption and leakage/static power. There’s been improvement in process technology, especially material innovations with High-K/Metal Gate (HKMG) and further advancements in Physical IP optimization for SoC implementation to gain greater performance and reduce power requirements.
And now, making it even easier are ARM Processor Optimization PackTM (POP) solutions on 40nm and 28nm processes. A POP is specifically tuned for a given ARM core and process technology to optimize both performance and lower power. There are three components of the POP: 1) ARM Artisan® Physical IP logic libraries and memory instances, 2) benchmarking report, and 3) implementation guide. These components enable SoC designers to tune their SoC implementation with a combination of options: 9-track or 12-track libraries, variety of Vt and channel lengths, and memories. Benchmark results have shown a 10-15% gain in performance and 20-40% reduction in static & dynamic power for the Cortex-A9 POP on 28nm. Actual silicon test chips and optimized silicon results achieved up to 1.6GHz. (For more information, download the POP whitepaper now.)
Additionally, there’s the Write-Assist feature for ARM Artisan® memory compilers on 28nm process, which allows for lower voltage operation below VDDmin. Further power savings are achieved when write-assist is enabled, and the memories are run at lower than standard nominal voltage. Both active power and leakage power can be significantly reduced by lowering the operating voltage to the minimum possible with this Write-Assist feature. For dynamic power, achieve up to 14% savings with iso-frequency operation and up to 35% savings with DVFS. For leakage power, achieve up to 25% savings.
What next-generation device will you be innovating? From the humble beginnings with the Apple Newton and continuous evolution in SoC designs, the latest smartphones are impressive mobile computing platforms. Maybe – with these low-power enablers – a smartchip implant could be a reality too.
Leon Chang, PIPD Strategic Accounts Marketing Manager, ARM, is based in Silicon Valley. Leon joined ARM in 2008 and manages a variety of strategic customers and foundry partners on the latest advanced processes and Physical IP. He’s fascinated with technology as it progresses further, pushing the limits of semiconductors. And of course, enjoying the latest devices from smartphones to tablets and home entertainment.
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