ARM Community: Early Power, Performance, Area Analysis & AMBA Designer: A Winning Combo - ARM Community

Power, performance and area or “PPA,” as it is called, has become a universally interesting topic to system-on-chip (SoC) designers around the world. Atrenta – an ARM Connected Community Partner and a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries – showcased a new and innovative design flow for early PPA estimation at last year’s ARM TechCon.

Design complexity now demands that all aspects of the design be co-optimized. If you reduce power, you will impact performance and area and so on. A holistic approach that balances all requirements of the chip is needed to deploy SoCs successfully.

Improving PPA by analyzing interconnect fabric earlier
Anyone will tell you that the interconnect fabric for the SoC has a profound impact on PPA. Knowing this, Atrenta turned its attention to AMBA Designer, ARM’s interconnect fabric generator, to develop our early PPA – or ePPA – technology concepts. What we demonstrated at TechCon was the ability to analyze a very early stage design, in which much of the IP was incomplete or only partially defined.

In this design, we generated several different versions of AMBA interconnect using AMBA Designer – versions with varying switch configurations, bus widths, etc. and then automatically floorplanned them to evaluate routing congestion, area, power and evaluated the possible operating frequency for each configuration, in the context of this early stage SoC. The demo was well-received, and we are now in active discussions with several customers to extend and refine the concepts of ePPA.

Any early analysis technology is only as good as its ability to accurately predict what will happen when the design is actually built. To prove we were onto something meant proving that our PPA predictions for various AMBA configurations did hold true once they were implemented with a production place and route tool.

Testing our theories with place and route
We set about doing this with a sophisticated simulation of an actual SoC and the interconnect fabric it would use. One aspect of interconnect fabrics is that they tend to “form fit” into the SoC, taking up space wherever available. That means the shape and aspect ratio of the same logical interconnect fabric will vary depending on the target SoC. To approximate this effect, we built two experiments with different aspect ratios, as shown in Figure 1.


Another effect to model is pin placement for the interconnect fabric. We utilized four different configurations for master (M) and slave (S) pin placement as shown in Figure 2.


With the various models in place, we then set about performing early PPA analysis on the various AMBA bus configurations and comparing our projected PPA data to the actual results from a place and route run with a production quality tool. The results were quite encouraging.

Our results
In the feasible regions of the fabrics, for the case of aspect ratio = 1:1, physical area estimates typically agreed to within 10 percent. Path delays were within 12 percent typically and leakage power differences were usually under 20 percent. For the case of aspect ratio = 1:2, physical area estimates were also typically within 10 percent. Path delays were usually within 10 percent in this case, and leakage power differences were usually under 20 percent.

This data is very encouraging, but what value does this bring to an SoC architect or early stage designer?

The real goal is to help grade bus configuration choices, while it is still possible to make substantive design choices. This ePPA solution has demonstrated an ability to evaluate, automatically, 20 different configurations, each at 3 different clock frequencies, each in the context of an early-stage SoC estimated floorplan, within 24 hours.

This kind of analysis can replace configuration guess-work with science. Tight correlation results increases confidence that both the science and the engineering are well-founded. And this confidence is an important ingredient for success in advanced SoC designs

Guest Partner Blogger:
Satish Soman, Chief Solutions Architect at Atrenta Inc. Satish has extensive experience delivering complex SoC designs at start-ups, medium size and large organizations. His expertise spans architecture, design, verification, silicon bring-up and field support. He has held senior management positions at LSI Logic, Digital Equipment Corporation and Nexabit (sold to Lucent for $1B). He holds 16 patents and received his MS in Computer Engineering from Syracuse University and BS in Electrical Engineering from IIT Bombay.

ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.

The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.