Memory Built-In Self-Test (BIST) has existed for as long as there have been modern SoCs. With today’s advanced SoCs containing literally hundreds and even thousands of SRAM memories, clustered in many memory subsystems throughout the SoC, both memory BIST as well as Built-In-Self-Repair (BISR) technology are increasingly important to insure the highest possible yield. System-on-chip designs are tailored for the optimal power, performance, area (PPA) and cost for a specific target application. To meet these increasingly challenging goals, designers are implementing solutions using multiple power domains, allowing the memory to run at high speed while conserving power in the periphery. These factors, combined with the different types of memories, including high density and high speed; single port, multi-port, register files and ROMs add to the complex task of ensuring the SoC performs to specification, and doesn’t limit yield in high volume production.
ARM has teamed up with Mentor to provide our customers a comprehensive and automated solution to address these issues and assure the highest level of SoC memory test for many of ARM’s Artisan® memory compilers at 65, 55, 40 and 28nm. ARM Artisan platforms at these process nodes support Mentor’s Tessent Memory BIST and BISR, as well as Fastscan for both standard cells and memory.
In determining the “right amount” of test and/or repair capability to include in an SoC design designers must perform a couple of different balancing acts. BIST and repair logic as well as memory redundancy add to overall SoC area and therefore silicon cost per die. Too much overhead results in, reducing the overall number of die per wafer. However, too little test and repair will result in more die per wafer, but with perhaps a lower yield resulting in little cost savings or even a higher die cost. Also too little BIST can result in poor test coverage and potential for test escapes and field failures.
The key factors to be considered in determining the optimal amount of BIST and repair logic may include;
- individual memory type,
- instance bit count,
- total SoC bit count,
- process maturity,
- process defect rate,
- defect rate specific to on-chip memory
Compounding the issue is the limited availability of such data from individual foundries, and the consistency by which the data is computed by each. Further, as the process matures, overall defect density generally improves with time and certain defect types may no longer occur. This allows the simplification and/or elimination of memory tests and thus reduction in test time. A field programmable memory BIST architecture is necessary to take advantage of this trend.
A final consideration for ARM was to support an open solution, available to all SoC design teams and supporting memory compilers from the wide range of memories types (SRAM, NVM, CAM, etc) available on the market. While both closed or memory supplier specific and internally developed solutions may provide extensive SoC test capability utilizing the latest algorithms, ARM believes only open, 3rd party BIST solutions insure support for SRAMs from all industry leading IP providers as well as advanced automation for tackling growing integration and test challenges.
Mentor’s Tessent Memory BIST solution provides the ideal solution to address all the issues noted here. The Tessent solution includes at-speed testing, diagnostics and repair of ARM Artisan embedded memories. Tessent MemoryBIST includes a comprehensive automation flow that provides design rule checking, test planning, integration and verification all at the RTL or gate level. In addition, all test capabilities created by Tessent MemoryBIST are fully supported by the Tessent SiliconInsight® interactive diagnostic tools.
Co-Authored by Stephen Pateras & Joel Rosenberg:
Stephen Pateras is Product Marketing Director for Mentor Graphics Silicon Test products. His previous position was vice president of marketing at LogicVision. While at LogicVision, Stephen also held senior management positions in engineering, and was instrumental in defining and bringing to market several generations of LogicVision’s semiconductor test products. From 1991 to 1995, Stephen held various engineering lead and management positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.
Joel Rosenberg, Platform Marketing Director, ARM, is based in San Jose, California. Ever since Joel received a “Heathkit Home Electronics Hobby Kit” for his 9th birthday, he has been intrigued by the endless possibilities of electronics systems design. Years later at university, he met a team of like-minded people and built homemade digital race car game simulators. In the early 1990s, Joel lead the Marketing for FPGA start-up Concurrent Logic which was acquired by Atmel. These days, Joel works on Physical IP Platforms for ramping nodes, BIST Marketing and drives programs with Silicon Aggregators.
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