The SOI community has worked for more than 20 years on fully-depleted transistors (Figure 1). Thanks to the limited silicon thickness between the gate and the buried oxide, the channel region is fully depleted (hence the name) below threshold, an inversion region forming above threshold to enable the current flow between source and drain. Unlike the planar bulk device, the fully-depleted device brings an additional control knob; the vertical electric field may be controlled by the silicon film thickness. A general rule of thumb is that the silicon film thickness must be a quarter of the gate length.
For 20nm node a 5nm silicon film is targeted which requires a tight control of the silicon film thickness, the manufacturing of such thin silicon films has already been proven. The fully-depleted device is still a planar 2D device. The silicon film thickness constraint may be released if two gates are used instead of one to fully deplete the silicon film; each gate contributing to deplete half of the film. The buried oxide is then replaced by the gate insulator to make the structure symmetric. This is where the manufacturing difficulty shows up; replacing the buried oxide by the gate thin dielectric is a challenge. A good solution to this problem is to rotate the full structure by 90o and the device then becomes a 3D device called Fin-FET (Figure 2).
In Fin-FET design the silicon film becomes a silicon fin sandwiched between two gates connected together where the current flows from source to drain through the silicon fin. The silicon fin width corresponding to the previous silicon film thickness of a fully-depleted device must be targeted around half of the gate length (10nm width for 20nm node). As the Fin-FET is a vertical dual gate structure, the crystal direction for the current flow is perpendicular to the planar case. The control of the silicon film thickness is replaced by the control of the fin width through lithography and etching, variation of this width results in threshold voltage variation.
The big difference with planar devices and Fin-FET is that the Fin-FET is a quantized device; the width of the transistor is defined by the fin height. This is obvious that the higher the fin the more current it will deliver; but the fin height is limited by the process implementation. The dual gate implementation uses a thick oxide to isolate the top of the fin from the gate generally referred to as Fin-FET. This thick oxide may not be used and the gate then wraps around the fin on three sides thus becoming a tri-gate device. The third top gate contributes to the control of the depletion of the fin and brings an improved control of the electric field which could be used to slightly increase the fin width.
This tri-gate implementation adds process complexity to ensure a good reliability of the gate insulator (requires rounding the fin corners). H and W being the height and width of the fin respectively, the Fin-FET width is 2H and the tri-gate width is 2H+W, the tri-gate may then deliver more current than its Fin-FET counterpart (still the different crystal orientations must be taken into account). The performance of the device is generally evaluated from the current per unit width that can be delivered (dividing the current by 2H or 2H+W) and many publications have shown the superiority of the Fin-FET or tri-gate based on this criterion when comparing to planar devices.
This is not necessarily relevant as these devices are 3D devices; the question from the circuit side is how many fins you can integrate per unit area. The only valid comparison is a circuit level comparison as not only the transistor density must be accounted for, but also the parasitic capacitances less in favor of 3D devices.
A very big advantage of fully-depleted devices (planar or 3D) is that you do not dope the channel region and then suppress the random dopant fluctuations (there may still be a parasitic doping from the residual doping of the silicon wafer). The threshold voltage is mainly fixed by the work function of the gate material. This directly impacts the variability and SRAM memories are expected to perform at low voltage with good margins. Fin-FET or tri-gate may be implemented on either bulk or SOI wafers. The bottom part of the fin resides on the buried oxide of the SOI wafer and the fin height results from the silicon film thickness of the SOI wafer. On bulk wafers, the fin is obtained through lateral isolation (STI), the height of the fin resulting from trench etching and partial refill. The bulk version requires an additional implant located at the bottom of the fin to avoid source to drain punch-through.
There is still work to be done, i.e. variability is expected to be different between SOI and bulk versions and needs to be quantified; the bulk version scalability needs to be investigated as the source-drain isolation needs to be maintained at the bottom of the fin while the SOI version is naturally isolated; SPICE models currently under development are needed to get an accurate description of the electrical behaviour of the 3D devices. However, 3D devices are clearly on the road for sub-20nm nodes…and Fin-FET’s time may finally be here.
Jean-Luc Pelloie, Fellow Director of SOI Technology, ARM, co-founded SOISIC in April 2001, the first independent company offering SOI IP blocks such as libraries of standard cells, I/O cells, and memory compilers. He joined ARM at the end of 2006 as Director of SOI Technology as a result of SOISIC’s acquisition and has become an ARM Fellow since then. He is currently a member of the executive committee of the IEEE SOI Conference and serves in the VLSI-TSA committee. He received his PhD degree in 1984 from the Institut National des Sciences Appliquées de Lyon. He managed for more than 10 years the SOI CMOS developments at LETI (Grenoble-France) where several technology generations were developed from 1.2 µm down to 90 nm. He worked for one year at the IBM Watson Research Center to manage an IBM/LETI SOI program in 93/94 and managed a TI/LETI program for advanced SOI CMOS in 99. His SOI expertise covers both fully-depleted and partially-depleted transistor architectures, including process integration, electrical characterization, Spice modeling and circuit design at transistor level. He has authored and co-authored more than 150 technical papers and is regularly invited to give presentations at renowned international conferences. He is currently contributing to the Physical IP development on the most advanced SOI process nodes.
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