ARM Community: Avoiding rush hour traffic jams in your SoC design - ARM Community

Thank goodness for the new packetization, virtual networking and clock gating features of the ARM CoreLink NIC-400. I’m fed up with hearing about spurious comparisons between a single humungous crossbar switch and NoC solutions. No design of any complexity uses a single cross bar switch! Modern SoC designs integrate large numbers of IP cores supporting the de facto industry standard AMBA AXI interface (open to all) using a network of small switches to allow very high operating frequencies and reduced routing congestion while still maintaining very low latencies and simplicity and flexibility of design.

Smart customers evaluate the alternatives to compare performance (bandwidths and latencies) vs. cost in terms of silicon area, routing congestion, power and price.

Packetization is great to increase wire utilization, but comes with a packetization/depacketization overhead that costs latency, gates and power. So should be used where it helps most to cross long distances with multi-cycle timings, for instance to remote IP cores or between switches. (NEW! ARM CoreLink NIC-400 has a Thin Links option exactly for this purpose).

Virtual Networks is another great idea to prevent a network blocking under heavy load. Loads vary enormously with usage case and it a very rare product today that can afford, competitively, to build a network so large and power hungry that it can never theoretically be overloaded. Virtual Networks prevent blocking of traffic so that even under very heavy loads vital tasks still complete on time and priority is given to tasks that give the best responsiveness to the user with graceful degradation of say the HD graphics if needs must. (NEW! ARM CoreLink NIC-400 has a QoS Virtual Networks option exactly for this purpose).

Power is always important these days. Interconnect fabrics form a very small percentage of the power budget compared to active processors and memory systems when an SoC is busy. However, during idle, or near idle, periods when many IP cores are powered down or asleep the interconnect fabric power is potentially significant. So mechanisms to prevent clocking of not just gates, but entire branches of the interconnect and its clock tree become useful. (NEW! ARM CoreLink NIC-400 has hierarchical clock gating built in exactly for this purpose).

So before jumping on the expensive, often royalty-bearing, NoC bandwagon look at the real alternative of Network Interconnects.

William Orme, Strategic Marketing Manager for System IP, Processor Division, ARM, is responsible for the next generation of system IP in the CoreLink and CoreSight product families. At ARM since 1996 he has lead the introduction of many new products, including the ETM and subsequent CoreSight multi-core debug and trace products. Prior to joining ARM, William has over 25 years in designing embedded systems from financial dealing rooms, through industrial automation to smartcard systems. William holds degrees in electronics and computer science as well as an MBA.