The first is the annual CEO panel, something that is becoming a GTC tradition. This one was entitled “Design Enablement Challenges and Future Solutions”. At this event, right after lunch, CEO’s, get together to talk about industry trends. ARM participated in the panel last year as well, with Simon Segars (EVP/GM of ARM’s Physical IP Division) representing ARM along with nearly the same other panelists. Also like last year, the panel was moderated by Mojy Chian from GLOBALFOUNDRIES, their Senior VP of Design Enablement. The panelists were:
- Warren East, CEO, ARM
- Lip-Bu Tan, CEO, Cadence
- Aart de Geus, CEO, Synopsys
- Robert Hum, VP and General Manager, “Deep Submicron” division of Mentor Graphics
This panel touched on a range of topics from market opportunities to competition between the EDA partners, etc. The auditorium was full to the brim and they had an overflow room downstairs as well, easily over 500 viewers if not more. Here were some of the key observations from the panel:
- Lip-Bu talked about the growing importance of data centers on the leading edge of applications like Facebook, Google, and something which is driving the trends in semiconductor design space.
- Warren spoke about the needs to optimize implementation and the increased pressure on achieving high GHz design. Specifically he highlighted the ARM Processor Optimization Packs (POP), emphasizing not only the importance of using optimizations such as the POP, but also telling people about the surprisingly high “attach rate” where many customers are already adopting this product to boost their competitiveness
- Robert from Mentor spoke about the growing importance of DFM. Linking to a talk earlier in the day (which showed GLOBALFOUNDRIES developing a pattern-based rule check to accelerate DFM check at 20nm) he mentioned the growing complexity in DFM at advanced nodes. He wondered how much of the DFM solutions will come from EDA vendors, the foundry, or through a collaboration of the two. The panelists also observed that the interaction of DFM and DFT needs to be a two-way street, where design feeds forward to manufacturing to say “these are important features or shapes the design needs” and manufacturing feeds back to design saying “these patterns are manufacturable”. [As an interesting aside, that two-way interaction is exactly what ARM has been doing in our work on advanced technologies for over 3 years now.]
- There was a lengthy discussion about analog design with some questions from the audience inquiring why analog design has not improved as rapidly. The conclusion was that analog is much harder in general, and harder to automate. They also pointed out that variation issues that can be addressed in digital design are much harder in analog design, such as the difficulty of getting two well-matched transistors for a current mirror. So designers are putting in extensive digital correction circuits to things like Op Amps to make them look like they have better characteristics at an analog level.
- There was a very interesting interchange between a few of the panelists, starting with Aart who talked about the fallacy of the work product in semi being the sum of our efforts. He proposed that the real answer is that it’s the product of our efforts: a zero in any area can kill all our work. A zero in manufacturing, design, IP, or EDA...any of those render the design a failure. They also talked about the perception that there’s a fixed pie of revenue available from designers, which they likened to a “five million dollar restaurant”, where each vendor is trying to get the most value from the customer. Aart finally summarized the business succinctly by observing that to win market share you must be “earlier, cheaper, or better”.
In the afternoon, ARM sponsored one of the parallel track sessions in which we hosted a panel discussion about mature technologies entitled “Is It Time for a Mainstream Revolution?”. Ed Sperling, a well-known industry journalist/analyst was the moderator. The panelists were:
- Naveed Sherwani, CEO, Open Silicon
- Walter Ng, VP, IP Ecosystem, GLOBALFOUNDRIES (Walter works for Mojy who I mentioned earlier)
- Vishal Kapoor, VP Marketing, Cadence
- Jeff Lukanc, Sr. Design Director, Integrated Device Technology
- …and myself
Here were some of the key topics:
- I began by introducing why ARM felt it was important to hold a panel on mainstream technology: In short, while everyone must work on advanced technologies to continue to push the leading edge, the mainstream nodes and applications are what “pays the bills” on a day to day basis while we’re still in the early days of advanced technologies like 28nm. We defined mainstream technology as 55nm and older.
- The panel spent quite a bit of time talking about how the industry is working to bring new value-added solutions to older nodes, such as 180nm. This could be driven from a number of motivations, but often it relates to cost reduction or power reduction. I gave the example of applications running on a small battery and thus requiring nanoamp-level leakage power. Similarly, power management chips are growing in importance as people are doing more to manage power on devices like smartphones. Mature technology nodes do a better job of managing higher voltages. Jeff from IDT mentioned a number of applications where very high voltage operation can be supported at 180nm, something which advanced nodes cannot achieve.
- There was a spirited discussion around EDA, which Vishal from Cadence and Naveed from Open Silicon going back and forth about the role of EDA. Naveed contended that it would be a real boon to the industry if mature node designs could be accomplished with only one or two designers “in an afternoon”. Vishal disagreed and says the industry has pushed for greater automation in every way, but the cost structure doesn’t make it commercially sensible for them to automate to that level, that it’s a necessary evil that the leading edge gets the initial focus. I observed that ARM continues to have customers push us in two different directions on mature nodes: Some of them want new IP but supporting older tool flows that customers already own, others want existing IP ported to newer flows. I also mentioned the increased need for power awareness in the models, ranging from the RTL level (such as Common Power Format), and down into the leakage modeling, where even some mature node designs are requesting advanced views like CCS Noise to carefully manage mixed signal designs.
- There was a debate among the panelists relating to the “second wave” fabs such as SMIC (even though this was GLOBALFOUNDRIES event…) where one questioner was inquiring why those fabs are not more successful at taking market share. We all agreed that the smaller fabs tend to be more expert at satisfying niche markets or specialty process flavors. One conclusion was that the leading edge fabs such as Chartered (which was later acquired by GLOBALFOUNDRIES) had a stronger history of investing in IP so customers had a complete solution available, to them. I commented that this trend seems to be changing, and these other fabs are beginning to invest more heavily in an IP ecosystem such as with ARM.
- I also brought up ARM’s extensive investment in two different areas. First, on the core side, ARM is pushing hard for the Cortex-M processor family of embedded cores, with over a billion units shipped to date. The Cortex-M processor family allows designers to benefit from a 32 bit modern programming environment and all the tools benefits it brings while in the footprint of an 8 bit microcontroller. This has the potential to shift over many designers from their existing 8051-based designs, and we’re seeing rapid adoption. The second point was that ARM is porting Physical IP innovations from the leading edge back to mature nodes, so there is a cascade of technology advances that those nodes can benefit from as well. As an example, I highlighted our new memory architecture from 40nm which we ported back to a range of mature technologies, improving density and power for those nodes.
You can also, check out Cadence’s summary of this panel here.
Both panels were very lively and raised a wide range of important topics germane to semiconductor designers across the spectrum. I’ll keep you posted with more upcoming events as we get into the busy fall season and we talk about our technologies around the world.
John Heinlein, Ph.D. is Vice President of Marketing, Physical IP Division, ARM, where he is responsible for directing both the Physical IP roadmap and engagements with key strategic customers. John has worked extensively with semiconductor leaders worldwide for many years, with a special focus on Asia. In his current role his goal is to drive adoption of ARM Physical IP across the SOC design community. Prior to joining ARM, John was with Transmeta Corporation for nearly 11 years.He holds a Ph.D. and M.S. in Electrical Engineering from Stanford University, and a B.S. in Computer Engineering from Carnegie Mellon University. John is an avid snowboarder and triathlete and former scuba diving instructor (he once swam with a whale shark!).
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