We are seeing dramatic growth in the data bandwidth in both mobile and fixed line networks. Cloud computing and video services are key applications driving this growth. 4G/LTE networks are transforming the wireless network experience for high-volume data users. Larger data centers with many virtualized servers allow large content providers such as Facebook, Google and Amazon to support many millions of users. To meet these demands, carriers are making significant investments in enhanced 4G networks and infrastructure required to support the huge growth in data traffic.
The latest silicon technology allows the integration of many cores onto a single SoC, dramatically reducing the number of components in a system. The processor cores can be closely coupled to hardware acceleration engines, external memory interfaces and high-speed networking I/O. The level of integration presents significant challenges to developers, who must ensure the use of shared resources does not reduce system performance. The key to this integration is the interconnect between the different cores and the other functional blocks.
Standard RISC cores, licensed from vendors such as ARM, have allowed system OEMs to quickly develop new solutions using third-party tools for software development. The introduction of licensed IP for a low-latency coherent interconnect will allow OEMs to develop more easily new solutions integrating multiple general purpose CPU and other cores. By working with well-established IP and SoC vendors such as ARM and LSI, system developers will have access to next-generation networking SoCs with a mix of CPU cores, hardware accelerators and, if required, their own hardware blocks.
The “Future Coherent Interconnect Technology for Networking Applications,” by Heavy Reading for LSI and ARM, explores the benefits of using a low-latency, coherent interconnect at the core of a next-generation networking SoC and reviews the market demand for next-generation network SoCs with multiple CPU cores and hardware accelerators. It details the technical challenges and one solution that is available to system developers for a coherent interconnect with integrated cache and support for DDR3 and DDR4 memories. The paper also describes a next-generation networking SoC architecture that is built around a coherent interconnect and available to OEMs as a standard product or custom solution.
Guest Partner Blogger:
Michael holds a bachelor’s degree in Electrical Engineering from the Pennsylvania State University and master’s degrees in Business Administration and Computer Engineering from Lehigh University.
ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.
The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.
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