Chih-Chieh Hsiao et al at the National Chiao-Tung University in Taiwan published the paper “A Hierarchical Primitive Lists Structure for Tile-based Rendering” at the 12th IEEE International Conference on Computational Science and Engineering in which they take a look at our next generation hierarchical tiling technology for keeping external memory bandwidth the lowest in the industry and thus save energy. Not only do they verify that this is pretty awesome stuff, they also explore some nifty ideas on how to improve it. Well done!
Designing graphics processors is a fantastic job. You get your hands dirty with the coolest technology on earth, and being smack in the middle of the action in the industry you get a pretty good view of what the world of technology will look like to the end-user years into the future. But there-in also lies the curse of this job. It takes a really long time from when we do our magic until it works its way through the value chain and the public get to know about it or hold a device in their hands. So it’s great to know that there are people out there that enjoy our technology even before the new products are in the shops.
And of course, it’s always nice to be cited.
Any other academic institutions out there working on our technology? We would love to know about it, email Tell.Us@arm.com.
Edvard Sørgård, Consultant Graphics Architect, ARM, is based in Trondheim, Norway. Ever since Edvard poked his first Commodore 64 balloon sprite he has been completely fascinated by computer graphics and hardware. Years later at university, he met a team of like-minded people and founded Falanx, the GPU company that ARM later snatched up to kick-start its hardware graphics offerings. These days, Edvard works on where to take Mali graphics next, while spending too much of his pocket money on Mali-powered devices.
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Jem Davies
on May 11 2012 06:46 AM
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