First of all, I must admit I wasn’t expecting them to set this family on the very lowend, even below their Cortex-M0 LPC1100 series. When we designed the Cortex-M0+ we aimed at offering at least as much the Cortex-M0 does, while adding capabilities to support low-power design even better and to address a wider scope of applications. I was anticipating an upgrade of the Cortex-M0 product line with even more features, memories and pins, with LP1100 and LPC1200 already on the market and the LPC1300 based on Cortex-M3. What could it become? Hmm… wait a moment... that brings to mind some similar brainstorming on a processor name… An LPC1200+? Lucky me, I didn’t bet as I would have lost!
Even if the name, the price point, the ease-of-use and the package smells very much like an 8-bit, NXP avoided any compromise on the processor. All Cortex-M’s are very flexible, and partners can fine tune their implementation by including or discarding options at Verilog level, so they could have opted for the minimal implementation. With LPC800, it’s the opposite and you get an almost full blown Cortex-M0+:
- The fast single cycle 32x32 bit multiplier
- The single-cycle interface, to which all GPIOs are connected
- The full NVIC with 32 Interrupts and 4 levels of priorities
- The SysTick timer,
- The Vector Table Relocation
- The Micro Trace Buffer for instruction tracing
So as you can see there is much more to the “ARM Cortex-M0+ 30MHz”, shown on the chip diagram:
The relocation of the vector table is a nice pick as this series has a fine flash page granularity of 64bit, combined together it will make IAP much more funky, enabling the application to still be able to serve critical interrupts while flashing, as long as you copied their service routine in the RAM. Talking about it, there is a generous RAM to Flash ratio of 1 to 4, offering 4kB RAM in the bigger configuration, so very nice for IAP and also great for instruction tracing, as it will be shared with Micro Trace Buffer when doing trace debug. When tracing, the MTB only needs to record two words per non sequential code access, after that the debugger can reconstruct all the program flow. This is very dense and will provide long depth when tracing.
Which Cortex-M0+ options were left down the road? The Memory Protection Unit, which for such lower end application makes sense to keep out. The small memory footprint limits the use-case of multi-application schemes running on this class of device, while the MPU is one of the biggest options in terms of gate count. NXP did not use the ARM WIC since it requires clocks to wake up the part. Instead, they implemented a clockless version. They used this idea with their new peripherals to offer wake up from them without any internal clocks. As an example, as an I2C slave the LPC800 can wake up when its slave address is matched. This means the part can be in power down mode consuming just leakage current and only wake up when there it sees its address. In addition, wake up from power down can come from pins, timers, and brownouts, offering many different ways to save power.
In all cases it’s a smart and fully loaded microcontroller that will get his way in many designs, and it even comes in a DIP 8-pin package! So as wrote my colleague Joseph one year ago for the LPC1100L launch: “Hey hobbyists, dust off your breadboards - DIP package is back!”
What else did I like? The switch matrix, the byte orientated I2C the state configuration timer, and the pattern matching on IOs. There have been very good blogs already posted since the launch, especially on the new peripherals, so I recommend having a look:
- Steve Bush article in Electronic Weekly
- Jack Ganssle’s blog with an deeper insight on the very cool pattern match feature
- MicroBuilder’s first though and following discussion
And also the following videos:
- Jan Jaap Bezemer Interview by Andy
- Nice intro videos, especially on the new Switch Matrix on LPCZone channel
- And a last one for the coffee break ;-)!
Thomas Ensergueix, CPU Product Manager, ARM. Thomas is leading the product management team in charge of the Cortex-M family of CPU as part of ARM’s processor division. Before joining ARM early 2012, he was active in the embedded area since the end of the 90’s, occupying multiple positions, and covered the whole spectrum of 8-bit to 32-bit architectures for smartcard ICs and microcontroller products.
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