The CoreLink CCN-504 Cache Coherent Network was announced at the Linley networking conference on October 10th, along with the DMC-520 DDR4 Dynamic Memory Controller are a perfect match for Cortex-A57 and Cortex-A53 for networking and server products.
The CoreLink 500 series of System IP components is further enhanced with the addition of the CoreLink GIC-500 Generic Interrupt Controller and the CoreLink MMU-500 System Memory Management Unit. The GIC-500 is designed specifically for Cortex-A57 and Cortex-A53. The MMU-500 is for IO device virtualization and works with Cortex-A15, Cortex-A7 and the newly announced Cortex-A57 and Cortex-A53 – more on these new additions later in this blog. The CoreLink 500 series system IP complements the highly successful AMBA® 4 protocol-compliant CoreLink 400 series.
Example Enterprise level Solution
For high-end mobile client applications, Cortex-A57 and Cortex-A53 are designed to connect to the CoreLink CCI-400 Cache Coherent Interconnect and the DMC-400 LPDDR2 and DDR3/DDR3L controller.
Example High-end Mobile Client Solution
Considering the challenges for a system designer tasked with creating multi-core, many core designs, along with cache-coherent interconnect the non-coherent interconnect must also address as a minimum:
- The need for QoS to ensure masters are adequately served
- Efficient access to DDR memory which is the main system bottleneck
- Focus on low power which remains key
CoreLink NIC-400 Network Interconnect is perfect for addressing each one of the above.
The ARM end-to-end QoS solution spans enterprise designs including CCN-504, NIC-400 and DMC-520, as well as mobile client designs with CCI-400, NIC-400 and DMC-400.
Details on the new CoreLink GIC-500:
The CoreLink GIC-500 Generic Interrupt Controller Detects, manages, virtualizes and distributes interrupts between ARM Cortex-A57 and Cortex-A53 series processors in multicore clusters.
Details on the new CoreLink MMU-500:
The CoreLink extends Cortex-A57 and Cortex-A53 series virtualization to other bus masters in the system. The MMU-500 is the second generation of system MMU products from ARM for IO virtualization. It translates addresses in hardware to accelerate hypervisor software virtualization of multiple guest Operating Systems (OS), it can also be used at OS driver level for functions such as memory defragmentation.
In conclusion, with the addition of the CoreLink 500 series ARM has a comprehensive roadmap of System IP for both mobile client, networking and server solutions. Noel Hurley, VP Marketing ARM Processor Division comments:
“ARM is committed to the success of its processors and system IP components in the mobile client and, networking and server market segments. Along with our traditional markets, as the amount of data increases significantly over the next 10-15 years, the demand for high-performance and energy-efficient network infrastructure and servers is increasing whilst power budgets remain static.”
Andy Nightingale, Manager of System IP products in the ARM Processor Division, has over 20 years experience in the technology industry. Andy is both a chartered member of the British Computer Society (BCS) and a chartered marketer with the Chartered Institute of marketing (CIM). Andy joined ARM in 1999 as a SoC Validation engineer and moved to product management in 2008. Andy is now responsible for the CoreLink System IP roadmap including the Coherent interconnect for big.LITTLE, NIC-400, DMC-400, GIC-400, MMU-400 and TZC-400 as well as the CoreSight debug and trace infrastructure.
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