Many microcontrollers embed one or more Cortex-M series processors. Due to their 32-bit architecture, compact instruction set, very small silicon footprint, upward code compatibility with other cores in the family, and power efficiency, the Cortex-M0 and Cortex-M0+ are the most attractive for mixed-signal applications, including smart sensors, RF transceivers, power regulators, LED drivers, barcode scanners, and motor controllers.
Integrating a processor with analog and mixed-signal peripherals brings additional design challenges. In addition to hardware, verification must include software as well. At the chip level, low level software drivers must be verified together with the peripherals. System designers often need to include analog signals in hardware/software co-verification.
Since May, ARM and Cadence have been working closely together on creating prototype of the mixed-signal design flow. Currently, the flow covers software development and mixed-signal simulation of the entire system including RTL for the core and behavioral models for analog and mixed-signal peripherals. The prototype models a system for controlling fuel injection pressure in an automobile using the Cortex-M0. It takes advantage of the Cortex-M System Design Kit (CMSDK) provided by ARM. The CMSDK is powerful companion to every Cortex-M processor, containing RTL blocks, related software drivers and working examples of digital sub-systems including interconnect and digital peripherals. The main program and CMSDK drivers are written in C language and can be compiled with any software toolchain supporting the Cortex-M series.
Pressure sensor and regulator and analog to digital converters are represented using highly efficient Real Number Models (RNM). These models represent the variable amplitude of analog signals in a discrete time domain so that the Cadence Virtuoso® AMS-Designer mixed-signal simulator is able to analyze them using only a digital solver, making simulation much more efficient. Digital signals control/feedback signals at input/output of the converters are saved and continuously refreshed in an analog interface registers and are accessed by processor through the AMBA Peripheral Bus (APB).
The test bench is created in Verilog-AMS, specifying the initial condition, nominal pressure and temperature dependence. The entire system at the top level is captured in the Virtuoso Schematic Editor, Virtuoso Analog Design Environment sets up and runs simulation, and the SimVision viewer monitors results. A special plug-in in SimVision enables cross probing between waveforms and processor instruction code so that for example, changes in waveforms can be observed while stepping through the instructions in C or assembler code.
The prototype demonstrates how an analog designer can simulate the entire system, including software controlling the processor while configuring and designing the analog part of the system. Similarly, a system designer/software developer can take into account analog parts of the system, early in the software development process.
The prototype is a small step in an exciting new direction that is bringing analog and system design closer, as many analog intensive MCUs require. To hear more on this topic, join us at ARM TechCon in Grand Ballroom C at Santa Clara Convention Center on Thursday, November 1, 2012 at 10:30am for a session titled “Fast-track to Embedded Design with ARM Cortex-M0+ and Cadence Mixed-Signal IC design flow”, jointly presented by ARM and Cadence.
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