The first key acknowledgment is that not only Analogue and Digital designers use different methodology and tools, but also they are likely to approach chip design with very different angles: detailed versus highly abstracted, interactive versus highly automated, which has strong implications on the tools themselves. Mixed signal tools have to be flexible enough and bridge the gap to unify both approaches and designer needs.
EDA Tools have tried to adapt to different mixed signal approaches taking either ways: “Digital-Centric” or “Analogue-Centric” methodology, respectively assuming that we are adding small Analogue to a predominantly Digital design or vice versa. They are also sometimes referred as “netlist-driven” and ”schematic-driven“, or digital-on-top and analogue-on-top. This offers mixed-signal capability but at the cost of forcing one designer view and methodologies over the other. This still work for limited complexity designs, but with the ever increasing integration, this model comes to its limit: what is the best methodology if you mix IP is about evenly among analogue and digital? Or what if your digital-centric SoC, now integrates many analogue IP taking half of chip area? How to sign-off mixed signal SoC’s using Static Timing Analysis (STA) or SPICE simulation? The solution proposed here is to extend and converge the two approaches into more unified methodology in which it is possible to use both schematic and netlist driven flows, concurrently. This new methodology is referred to “mixed-signal on top”, and enables Digital and Analogue designers to more closely collaborate on crafting mixed-signal SoC using both analogue and digital techniques for floor-planning, pin optimization, routing and sign-off analysis. Bottom line for the user: less iteration during design, shorter design cycle, and smaller die size can be achieved.
Beyond the design and routing, the verification and simulation must also be able to cover both the digital and analogue, to ensure the test coverage, to provide accurate power consumption estimations also taking into account cases with multiple power domains. The Unified Verification Methodology (UVM) which seems to be well adopted by digital designers is being extended to analogue and mixed-signal by defining Unified Verification Component (UVC) suitable for monitoring performance and measuring coverage for analogue signals as well. On the power side the Common Power Format has been extended to cover also the analogue modules, leading to low-power aware AMS simulation, and enabling static low-power checks.
One very impressive part of the presentation was the demonstration of a mixed-signal simulation of a design including analogue blocks and Cortex-M0, based on the Cortex-M System Design Kit (CMSDK). The design was made in Virtuoso Schematic Capture, completely simulated using Cadence’s integrated mixed-signal simulator, and SimVision tool is used to visualize results. This gives a user great visibility of the overall system by displaying analogue values, digital signals and linking them with the C source code running on the Cortex-M0 processor.
An EDA tool like Virtuoso® and EDI from Cadence are now enabling the concurrent “mixed signal on top” design approach; and this definitely represents a major leap forward. The extended tool capabilities are one part of the story. To make the best out of it, designers should acknowledge that the walls which used to be imposed by the tools between analogue and digital are now vanishing. It enables a closer exchange between the analogue and design teams, raising the chances of first silicon success, so let’s take advantage of it! Last but not least, Cadence thanked all participants with the recently released “Mixed-Signal Methodology Guide” book, written by mixed-signal experts from Cadence and other companies.
More information on the Cadence EMEA Mixed Signal Tour can be found here. There will be also a related session on ARM TechConTM 2012 in Santa Clara.
Thomas Ensergueix, CPU Product Manager, ARM. Thomas is leading the product management team in charge of the Cortex-M family of CPU as part of ARM’s processor division. Before joining ARM early 2012, he was active in the embedded area since the end of the 90’s, occupying multiple positions, and covered the whole spectrum of 8-bit to 32-bit architectures for smartcard ICs and microcontroller products.
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