ARM Community: Reducing Verification Challenges on ARM's ACE Coherency - ARM Community

ARM's Cortex-A15 MPCore processor continues to gain licensees as it is so well suited for mobile computing applications, probably the fastest growing semiconductor market space on the planet. Cadence customers tell us they selected the Cortex-A15 largely because it provides multiprocessor support and hardware based coherency while consuming only a small amount of power. In our experience the majority of Cortex-A15 designs are also adopting the new AMBA 4 ACE protocol due to their need for a fast and reliable coherency scheme.

To help potential Cortex-A15 designers learn more about AMBA ACE, ARM and Cadence partnered to develop a video about ACE and ACE verification. It's only about 10 minutes long, I encourage you to view it. In addition you can read my previous blogs discussing the need for hardware based coherency and what to look for in best in class verification solutions for ACE verification.



While AMBA ACE compliance is challenging to verify, the even bigger verification challenge is ensuring the design is actually coherent. We are seeing that nearly all ACE-based designs also incorporate fabrics such as the ARM CoreLink CCI-400 and/or NIC-400. This is where Cadence's complete ACE verification solution will provide superior value to you. For this type of design it's necessary to have three verification tools all working in conjunction. They are the ACE Verification IP itself, the Coherent Interconnect Monitor, and the Intelligent ACE Scoreboard. Only with all three working together will you be assured of achieving end-to-end design coherency.

Cadence's solution addresses all the common ACE/coherency verification challenges. For example it will:

• Create the necessary scenarios needed to mimic processor and memory behavior including snooping operations
• Verify that data coherency is maintained (i.e. ensure that only one copy of each data item is valid)
• Ensure that all simultaneous write/snoop combinations are managed correctly
• Ensure that no scenarios create deadlocks

Please let me know what’s on your mind. How are you planning to tackle ACE based SoC verification? What challenges are you most concerning to you?

Guest Partner Blogger:
Pete Heller is Senior Product Line Manager for Verification IP (VIP) and Interconnect at Cadence and has played a key role in the growth of Cadence’s VIP business. Mr. Heller holds both a BA in Computer Science as well as an MBA from Indiana University’s Kelley Graduate School of Business.

ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.

The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.