The Next Challenge: Ensuring ACE Coherency Schemes are Fully Verified
ARM has now delivered the ACE specification. That’s a great start. However, with so many processing elements and memories in today’s SoC’s, how does an engineering team go about verifying cache coherency in an ACE-based design? It’s not realistic for an engineer to simply read the ACE specification and expect to get the design right. They need specialized verification tools, known as Verification IP (VIP), to ensure their cache management scheme is correctly implemented and fully exercised.
The Keys to Verifying ACE-based, Cache Coherent Designs
There are three major capabilities necessary to verify ACE-based designs. They are:
1. Mimicking all possible scenarios to cover the full verification space
2. Ensuring coherency and system compliance with the ACE specification
3. Measuring coverage and ensuring verification completeness.
The remainder of this blog describes what to look for when considering ACE verification solutions and specifically what is required in ACE Verification IP (VIP).
Not Just Any VIP Will Do
Verifying ACE coherency is well beyond the ability of directed testing, the basic verification scheme most designers employ. Directed testing requires that engineers write a specific test for every possible scenario that could occur within the system.
Instead, a verification technique known as constrained random stimulus generation is required. The VIP must “think” through the enormous state space and generate stimuli for the engineer that will yield coverage for all the relevant scenarios. This unburdens the engineer from this humanly impossible task and enables her to focus on the key risk areas exposed by the VIP. With stimulus taken care of, the VIP must also provide a metric driven verification solution which is used to evaluate verification completeness.
The best practices in doing ACE verification are to first use the VIP to ensure that all the individual masters and slaves comply with the ACE specification. Then the VIP must be teamed with a separate interconnect monitor that checks all the traffic on the interconnect fabric. The combination of VIP and interconnect monitoring is necessary to ensure coherency of the full SoC.
Cadence Delivers First Full Solution for ACE Coherency Verification
To help engineers tackle the daunting ACE verification challenge Cadence has added the ACE Verification IP (VIP) to its broad VIP Catalog. The ACE VIP, used in tandem with the Cadence end-to-end interconnect monitor (ICM), designers have the first full solution for ACE coherency verification. The Cadence ACE VIP solution provides the stimulus, checking, and functional coverage reporting and monitoring needed to give designers the confidence that their full SoC design is truly coherent and in compliance with the ACE specification.
This is the result of an extensive collaboration with ARM to ensure the VIP meets with ARM’s standards. Cadence has incorporated ARM’s ACE assertions and coverage points into our regression suite to ensure there is only a single interpretation of the ACE specification. In addition, Cadence has worked with ARM’s leading Cortex-A15 customers to prove out the VIP’s value in advance of the ACE announcement to ensure its readiness for mainstream use.
You can find additional information about ARM’s ACE protocol here. For additional information regarding Cadence ACE verification IP visit the AMBA VIP web page.
Guest Partner Blogger:
ARM welcomes its wealth of Partners in the ARM Connected Community (CC) to submit guest blogs to be published on our multiple community blogs. If interested in participating please submit email inquiries to Tell.Us@arm.com.
The ARM Connected Community (CC) is an extensive ecosystem covering all aspects of ARM processor-based design, from chip implementation through to system and device design. The CC provides a platform for collaborative innovation, with multiple types of forums for members to work with one another, and with customers, to solve industry challenges, all with the purpose of enabling designers to focus on differentiating features and an accelerated time-to-market for ARM powered solutions.
0 Comments On This Entry
Please log in above to add a comment or register for an account
Peggie: University of Oxford, UK - Shell Eco-Marathon Finals in Rotterdam
on May 22 2013 02:31 PM
Cortex-M0+ a year after: smaller, thriftier and smarter!
on May 20 2013 02:59 PM
The Continuing Hazards of Dhrystone
on May 16 2013 10:24 AM
Make versus buy: it's about risk management!
on May 15 2013 02:29 PM
Accelerated Internet of Things (IoT) development with ARM mbed and Xively
on May 14 2013 12:21 PM