ARM Community: Coherency: the key to boosting future tablets, smartphones and digital TV’s - ARM Community

The ability to integrate many processing engines in a more efficient way by sharing on-chip data is the goal of all system architects and designers working on complex heterogeneous multicore SoCs.

For that reason I’m excited to tell you that we have today announced the AMBA 4 ACE specification at DAC and we have a number of ARM Partners licensing and integrating this product into their next Cortex-A15 design.

Also I’m pleased to be able to let you know that last week we released the CoreLink™ CCI-400, ARM’s first Cache Coherent Interconnect. So what’s special about this interconnect? Well it implements the new AMBA® 4 ACE™ standard with AXI Coherency Extensions (read all about it in this blog from Bruce Mathewson).

With the new CCI-400 product wired up to the latest ARM Cortex™-A15 and Mali™-T604 we’re offering ARM Partners the performance boost required for next year’s tablets, super-phones and maybe even super computers.

CCI-400 can extend symmetric multi-processing with the Cortex-A15 processor from four cores within a single cluster, to two clusters giving a total of 8 CPU cores. This opens up new markets where more processing is required such as networking applications and servers. CCI-400 also has three dedicated ports for one-way or I/O coherent devices using ACE-Lite™ such as the Mali-T604 graphics processor. This means that these devices can read directly from on-chip processor caches, rather than taking the long and power hungry route to external DDR.

One thing I would like to highlight is the potential for performance scaling and power efficiency gains. Historically cache maintenance has required a lot of software overhead to clean and invalidate caches when moving any shared data between on-chip processing engines. Hardware coherency removes this requirement and this allows the processor to enter a lower power state or move to the next useful task instead of house keeping. Also with less cleaning of caches to external memory we reduce power and bandwidth consuming DDR accesses, and get higher hit rates to the cache.

CCI-400 benefits are not limited to coherency, this product also supports the virtualisation extensions including a low latency connection to a system MMU (such as CoreLink MMU-400) to allow virtualisation of hardware devices. This could be used to take advantage of multiple OS’s running on the same hardware, or simply a more efficient way to share limited physical memory.

CCI-400 is the first of a range of coherent interconnect products that ARM is developing. Just make sure your next SoC architecture considers the benefits of a coherent interconnect!

For more information on AMBA 4 ACE check out the following:

• Watch a webinar on AMBA 4 ACE technology
• Read whitepapers from ARM and Jasper
• Download the AMBA 4 ACE specifications (PDF - requires log-in)
• Understand more about system coherency:
  • Think Globally, Act Locally: Why coherency matters to smart mobile devices
  • Fitting Coherency for many-core systems with shared data
• System validation products are provided by ARM’s partners including Jasper and Cadence

Neil Parris, Interconnect Product Manager, ARM. Neil joined ARM in 2000 working on system architecture, consulting projects and ASIC design built around ARM processors. Following the design role Neil supported a number of major customers as part of the US Field Applications team before moving to the current role of Interconnect Product Manager. Neil holds a 1st class Masters degree in Electronic Engineering Systems from the University of Sheffield, UK.