ARM Community: Get an Exemption from Preemption with RTOSs running on ARM Processors - ARM Community

Most real-time operating systems (RTOS) that support ARM processors use preemptive scheduling for real-time response. This is due to the fact that ARM processors are commonly used in consumer electronics, medical devices, and industrial control, all of which require at least some degree of real-time performance. But while preemption delivers responsiveness by enabling high-priority tasks/threads to use the CPU immediately as soon as they need it, in many cases this can add unnecessary overhead and actually reduce system throughput. Recent Computer Science research (see below) has shown that “Preemption-Threshold Scheduling” (PTS), introduced by Express Logic in 1997 in our ThreadX RTOS, can reduce context switch overhead, while still meeting all real-time schedulability deadlines.


In this excerpt from Jejurikar and Gupta’s 2004 study, we can see that PTS reduces context switches by 70% - 90%.

What’s interesting about PTS is that it eliminates context switching in many cases, while still enabling the system to meet real-time deadlines 100% of the time. But, embedded real-time systems that use ARM processors also demand massive throughput. For example, mobile devices handling streaming video are extremely dependent on high throughput, without which they could never provide the rich entertainment we have come to expect from our smartphones and tablets.

But, context switches use valuable CPU cycles, and this can prevent the system from meeting its throughput requirements, even with a powerful ARM9 or Cortex CPU. In fact, context switches on ARM processors tend to be faster (require fewer cycles) than on other processor architectures, because ARM processors use a relatively small register set, enable the loading/storing of multiple registers (including PC/SPSR) at a time. ThreadX further optimizes context switching on ARM by not saving/restoring the context when no thread is running (and therefore there is no preemption). And, Cortex-M parts are further optimized to save compiler scratch registers as part of the interrupt fetch on the interrupted thread's stack, making it unnecessary for the RTOS to do so.

Given the cycle cost of context switches, and the fact that context switches are an inevitable consequence of preemption, how does the developer support preemption and still achieve high throughput? With PTS, only the context switches that are essential to meeting deadlines are performed, while others are denied, even if it means letting a low priority thread continue to run while a higher priority thread is waiting. This reduces system overhead by completely eliminating many costly context switches, while preserving the system’s ability to meet real-time scheduling requirements. No matter how fast a context switch is performed, skipping it entirely is even faster!

For those looking for the full story, several articles and white papers are available on this topic:

"Lower the Overhead in RTOS Scheduling"
Professor Alexander Dean, Ph.D., Embedded Systems Design Magazine, March, 2011

“Scheduling Fixed-Priority Tasks with Preemption Threshold”
Wang, Concordia University, and Saksena, University of Pittsburgh

“Preemption threshold scheduling: Stack optimality, enhancements and analysis”
R. Ghattas and A. G. Dean, RTAS ’07: Proc. of the 13th IEEE Real Time and Embedded Technology and Applications Symposium, 2007

“Reducing Stack with Intra-Task Threshold Priorities in Real-Time Systems”
G. Yao and G. Buttazzo, Proceedings. of the 10th Int. Conf. on Embedded Software, 2010

So, developers - How do you balance the tradeoff between real-time responsiveness and maximum throughput in your ARM-based design? Would PTS possibly offer an attractive means of achieving the balance you desire? Please let us know your thoughts!

John A. Carbone, Vice President of Marketing for Express Logic, has 35 years experience in real-time computer systems and software, ranging from embedded system developer and FAE to vice president of sales and marketing. Mr. Carbone’s experience includes embedded computers, array processors, attached processors, development tools, and both commercial and proprietary real-time operating systems. Mr. Carbone has a BA degree in mathematics from Boston College.

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