ARM Community: Optimizing ARM SoCs through Core, Memory, Power and Process Improvements - ARM Community

ARM sponsored a session at the ARM Technology Conference (Techcon) this year to discuss critical implementation issues for SoC design ranging from high performance ARM processors, SRAM design, SOI, Power and Noise analysis, DFT and BIST, among others. The session featured speakers from ARM, Apache, IBM and Mentor. This aligned with the newly restructured Techcon where the first day focused around silicon design and implementation. It was a fantastic session, of which I had the honor of serving as session chair. The talks were standing room only, with people out the door in a number of cases.

Technology challenges demand a system-level focus
We began the day with introductory remarks from Dipesh Patel, the VP of Engineering, ARM Physical IP Division, giving an overview of the technology challenges the industry faces. He observed that a system-level focus is needed to deliver a compelling solution. In particular, that the significantly increased implementation complexity requires a solution that starts at the core of the chip and spans out through all the major subsystems, graphics, video, system interfaces, and the Physical IP on which those platforms are implemented.

Dipesh Patel
IBM’s latest SOI technology at 32 nm
Then Gorden Starkey from IBM gave a diverse overview of the latest progress in Silcon-on-Insulator technology (SOI). The room was absolutely packed with folks wanting to hear about SOI, especially in light of IBM's announcement the day before of their new 32nm ASIC platform based on SOI. He showed how the unique transistor structure of SOI can enable designers to get up to

Gorden Starkey
30% more performance from their design, take 25% smaller area for the same performance, or the same performance at substantially lower leakage. Pretty exciting stuff and it's made better by IBM's eDRAM technology that SOI enables where high density true 1-T DRAM can be embedded effectively alongside logic devices, something bulk CMOS cannot match.

Achieving continued scaling at advanced technology with Artisan Memory Compilers
Next Gus Yeung, Fellow, ARM Physical IP Division described ARM's work on advanced memory architectures. He described the systematic way that ARM analyzes the market needs and foundry process technologies to deliver continued improvements in memory design. He laid out his design goals with the simple mantra "2, 2, 2": Each new semiconductor generation should deliver 2x the performance, 2x the density and (yes and, not or) 2x more power efficiency. Despite how challenging this goal is, he showed how ARM has been able to match and even exceed those goals in our recent 32/28nm Physical IP platform.

Gus Yeung
Managing Power and Noise in leading-edge SoCs with Apache tools
Aveek Sarkar, Vice President of Product Engineering & Support, Apache Design Solutions, spoke next about how power and noise are becoming critical issues for advanced designs. Apache has become one of the industry leaders in tackling this problem with their suite of tools that studies this problem at even level of design. Most notably, their flagship RedHawk product enables designers to do integrated power, extraction, and transient simulations and quickly pinpoint root causes, something which is becoming both increasingly important and also challenging.

Aveek Sarkar
Achieving 1 GHz+ dual core A9 performance at 32nm with Cortex-A9 Processor Optimization Packs
Next up was Jinson Koppanalil, Staff Engineer, from the ARM Processor Division, accompanied by Dermot O'Driscoll, Manager of Implementation and Methodology. This talk focused on ARM’s recent implementation of a complete ARM Cortex-A9 test chip on Samsung's 32nm LP process technology. This chip was designed in late 2009 through 2010 in ARM's Austin design center and was primarily focused on proving the performance capabilities of the Cortex-A9 and ARM Artisan Physical IP on 32nm. This project especially leveraged the Cortex-A9 Processor Optimization Pack ("POP"), which contains specially optimized ARM Artisan Physical IP for the Cortex-A9. That same day, the Processor Optimization Pack product line was launched overall, as was the specific 32nm POP this development project helped produce. These optimizations will help ARM Partners achieve over 1.0 GHz operation, which our early silicon results prove is definitely possible.

Jinson Koppanalil
ARM and Mentor team up on memory BIST to maximize yield and minimize overhead
The final session was a tag team between Stephen Pateras, Product Marketing Director, Mentor Graphics, and Teresa McLaurin, DFT Manager and Technical Lead, ARM. Teresa explained how ARM is working with Mentor to ensure that a robust memory test and repair solution available to our mutual customers, to enable high quality levels and maximum product yield. In particular, she explained how ARM processor cores include an optimized MBIST interface that provides external access to all memories embedded within the core at lower overhead than typical solutions. Steve showed how Mentor's Tessent MemoryBIST provides an automated flow for generating and inserting memory BIST and repair IP that is fully integrated with the ARM processor MBIST interface.

Stephan Pateras

Teresa McLaurin
It was a whirlwind day with presentations spanning many of the critical difficult areas for advanced SoC design. We were grateful to the rich audience turnout and to the hard work in preparation by the speakers.

John Heinlein, Ph.D. is Vice President of Marketing, Physical IP Division, ARM, where he is responsible for directing both the Physical IP roadmap and engagements with key strategic customers. John has worked extensively with semiconductor leaders worldwide for many years, with a special focus on Asia. In his current role his goal is to drive adoption of ARM Physical IP across the SOC design community. Prior to joining ARM, John was with Transmeta Corporation for nearly 11 years.He holds a Ph.D. and M.S. in Electrical Engineering from Stanford University, and a B.S. in Computer Engineering from Carnegie Mellon University. John is an avid snowboarder and triathlete and former scuba diving instructor (he once swam with a whale shark!).