The external memory bottleneck can jam up the performance of your high performance processors and drain unnecessary power if your system design is not up to scratch. It’s an unfortunate fact of life that the external DRAM bandwidth is strictly limited by both cost and power budgets for any mobile consumer device and many tethered devices too.
Step 1: fit a memory controller that gets the maximum utilisation out of the given frequency and width of the DDR port. Step 2: use a priority driven QoS arbitration scheme that grants a clear path to low latency traffic while still giving the maximum available bandwidth to the media processors. Step 3: choose a high bandwidth, low latency, non-blocking interconnect. Step 4: choose processors that have a lower memory bandwidth requirement for the high performance required.
Find out what ARM with its new CoreLink system IP can do to when coupled with the latest Cortex and Mali processors at the ARM Techcon in Santa Clara on Nov 11th at 12:00 noon in the ARM theatre on the show floor or at 2pm in the conference session: ‘Negotiating the Maze - getting the most out of memory systems today and tomorrow’
William Orme, Strategic Marketing Manager for System IP, Processor Division, ARM is responsible for the next generation of system IP in the CoreLink and CoreSight product families. At ARM since 1996 he has lead the introduction of many new products, including the ETM and subsequent CoreSight multi-core debug and trace products. Prior to joining ARM, William has over 25 years in designing embedded systems from financial dealing rooms, through industrial automation to smartcard systems. William holds degrees in electronics and computer science as well as an MBA.
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