ARM Community: Fitting Coherency for many-core systems with shared data at ARM Techcon - ARM Community

Hardware cache coherency offers complete transparency to the software developer, removers the need for cache maintenance and enables higher cache utilization, raising performance and saving power.

Why do I need hardware coherency in my ARM system? To meet the environmental challenge of ever more powerful home and enterprise products that consume less energy and don’t require forced air cooling, the SoC world is embracing many-core computing: clusters of multi-core CPUs together with multi-core GPUs or arrays of DSPs. Many smaller cores running at lower frequencies offer a better power profile than 1 or 2 CPU monsters. The software running across these heterogeneous cores is also changing, to share more data. What was a dedicated games engine is now helping out with line drawing and textures in all sorts of software from the GUI to image recognition. Similarly, the CPU plays an important role in graphics software from implementing OpenGL drivers to the physics engine for CGI.

Sharing data correctly can be achieved in three ways. The simplest, keeping all shared data in common off-chip memory has a very high performance and power consumption penalty as the data is not cached. This also affects other software by clogging up the external memory interface with unnecessary off-chip traffic. Software cache maintenance, flushing shared areas back to main memory is a step in the right direction but is expensive in CPU processing time, energy and is notoriously bug prone. Hardware cache coherency offers complete transparency to the software developer, removers the need for cache maintenance and enables higher cache utilisation, raising performance and saving power. What! A solution that simplifies software and improves my performance and power. Brilliant.

To find out about how ARM with CoreLink system IP have introduced coherency between CPU clusters, GPUs and other I/O come along to the system IP theatre session on the show floor at 12:00 noon on Nov 11^th or the how ‘The Future of Embedded Graphics’ gains from system coherency at 1pm on Nov 10^th at ARM Techcon in Santa Clara.

William Orme, Strategic Marketing Manager for System IP, Processor Division, ARM is responsible for the next generation of system IP in the CoreLink and CoreSight product families. At ARM since 1996 he has lead the introduction of many new products, including the ETM and subsequent CoreSight multi-core debug and trace products. Prior to joining ARM, William has over 25 years in designing embedded systems from financial dealing rooms, through industrial automation to smartcard systems. William holds degrees in electronics and computer science as well as an MBA.

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