ARM Community: Maximize Performance with ARM’s Interconnect NIC-301 & ChipEstimate at DAC - ARM Community

It’s exciting to think that so far we’ve licensed ARM's CoreLink products including Network Interconnect (NIC-301) to over 100 companies. CoreLink designs have since shipped in millions of units of consumer electronics across all segments. The latest product to join the family is the QoS-301 Advanced Quality of Service option for NIC-301 allowing customers to maximize performance and minimize latency and power. Check out the ARM and Cadence video presenting the combination of CoreLink IP and chip estimation tools at DAC last week in Anaheim:



The CoreLink Network Interconnect is highly configurable, and can be optimized to suit the requirements of the masters, memory system and IOs it is linking together. NIC-301 is designed and built around a network of AMBA interconnect switches, a ‘must’ for small geometries and increasing numbers of IP cores. Each switch can be configured for different bus widths from 32 to 256 bits wide, and for different clock domains with automatic insertion bus width and clock conversion bridging. In the latest release, we’ve included new bridges with reduced arbitration & translation latency across clock domains, data widths and AMBA protocols.

ARM and its Partners’ research and expertise has proven that on-chip data flows have a number of requirements that need to be met concurrently through the interconnect and memory controller. Some common examples are maximum latency for display controller to prevent dropped frames, minimum bandwidth for DMA transfers and best effort masters such as latency sensitive CPUs. The neat thing about the QoS option for NIC-301 is that it manages data traffic at entry to the network interconnect using targeted hardware resource for critical components. We’ve proven that QoS, in combination with the CoreLink Dynamic Memory Controllers (DMC-34x) minimizes average latency for best-effort masters, and guarantees bandwidth & latency for real-time traffic.

Once configured, NIC-301 and QOS-301 can also be loaded into Cadence InCyte Chip Estimator tool, along with other AMBA-based SoC components to provide the system architect with initial power and area estimates very early on in the design cycle, enabling rapid what-if analysis across the design solution space.

Andy Nightingale, a product manager in the Fabric IP business unit of the Processor Division, ARM, has over 20 years experience in the technology industry, now in his 11th year at ARM based in Cambridge. Andy started ARM as a SoC Validation engineer and moved on to generating AMBA protocol compliance suites before architecting the AMBA Designer tool now used to configure and generate CoreLink Fabric IP including the NIC-301 network interconnect and DMC-34x dynamic memory controller products. Andy’s product management responsibilities include Fabric tools and verification IP with a bias on enabling interoperability with leading EDA vendors.

Shortlink to this post: http://bit.ly/df3t80