ARM Community: ARM @DAC: GF Collaboration, 32nm Physical IP, Early SW Development Tools - ARM Community

Tuesday was another full day of ARM everywhere at the Design Automation Conference (DAC) with a special emphasis on the Physical IP products. And my blog from Monday’s (ARM @ 47DAC: IP Collaboration, MCUs, Software Tools, Memory BIST and Zydeco) didn’t even cover all of my activities from Monday. Today’s highlights include:

• GlobalFoundries (GF) keynote From Contract to Collaboration: Delivering a New Approach to Foundry by CEO, Doug Grose
• ARM IP Talks at ChipEstimate Booth
• Access Innovation Luncheon with ARM, Common Platform, Synopsys and GF: 32/28nm Delivered with HKMG
• Achieve Early Software Development Pre-Silicon with ARM and EDA Tools
• ARM DAC press news
• ARM Connected Community Partners

GlobalFoundries: Collaboration is the Key

Richard Goering wrote an excellent review of the keynote ‘calling for a new, globally dispersed foundry model with deep collaboration,’ so I will focus on some additional areas that stood out for me. The collaboration theme resonates clearly for me as the ARM business model is predicated on the success of our ecosystem, the ARM Connected Community (CC), and its successful collaboration to create technology and end devices that our customers and customers’ customers want. In fact, the tagline of the CC is ‘Connect, Collaborate, Create’ (as shown on the 40+ ARM Partners participating at DAC.) We value the collective wisdom and talents of our Partners and are proud of the diverse ARM Powered Products that continue to be created each day. Doug Grose declared that “Collaboration is the watchword for innovation today.”

As an example of this collaboration, Grose emphasized the work with the ARM Cortex-A9 and ARM’s physical IP. This collaboration is a next-generation platform for smart mobile devices that was developed with 28nm bulk process technology with second generation HKMG that resulted in more than 2x gate density of industry standard 40nm. This platform set the new standard for performance and power in mobile applications. The gains by the platform approach were achieved because the design and process development was done in parallel with a foundational SoC design platform with ARM’s physical IP. Grose described this baseline SoC platform as a foundational solution that customers can customize allowing the flexibility benefits found in the traditional foundry model.

ARM IP Talks at ChipEstimate Booth

The theme of flexible and high quality physical IP continued as I traveled to listen to Wolfgang Helfricht discuss the ARM portfolio of physical IP on the DAC floor. He discussed the now familiar themes of:

• ARM physical IP is the leader at 32nm today with released production quality 32nm standard cell libraries
• ARM has an extensive repertory of IP at various process nodes in addition to 32nm available today at http://designstart.arm.com

Tonight I came back and read Richard Goering's blog on Dr. John Heinlein’s keynote and viewed his video interview from Monday that covered themes of:

• What is ARM’s portfolio of products?
  

• For those who are unfamiliar with ARM Physical IP, I especially liked John’s analogy: ‘we sell the bricks & mortar to the house.’
• How do we solve the power challenge?
• When should designers use HKMG versus SOI libraries?
  

• On Monday, Dipesh Patel of ARM spoke on a panel in the Cadence booth on SOI (IP, Tools, Readiness, Ecosystem Growing, Libraries Panel). In addition to John’s comparison of HKMG and SOI, Dipesh added that the advantages of SOI libraries are that for a given process, SOI can achieve higher performance for the same power or achieve lower power targets without a hit on performance. (One of the Monday events that I never got around to reviewing.)
• What RDRs (restrictive design rules) has ARM implemented at 32nm?
• When and how will customers migrate to 32/28nm?

Access Innovation Luncheon with ARM, Common Platform, Synopsys and GF: 32/28 nm Delivered with HKMG

Not yet having had my fill of hearing about our physical IP products, I headed over to the Marriot for a box luncheon about the announcement from Monday. The overall theme of the luncheon was simple: We delivered. At last year’s DAC, ARM, the Common Platform (CP) members (IBM, Samsung and Chartered) and Synopsys stated that in a year they would deliver a fully functional, tested flow for 32/28nm. Today’s luncheon was to celebrate the delivery and discuss the benefits gained.

The three foundries (GLOBAL FOUNDRIES represented Chartered) discussed their various successes at the new nodes and invited participants to come to the booth to see the actual silicon. The crowd was generally impressed with the detailed gains that each foundry achieved. Synopsys articulated their gains from the fully functional and tested reference flow.

Dr. John Heinlein spoke on behalf of ARM and began with the general overview of the ARM portfolio of “Processors to Pads” that enable world-class SoCs. The ARM physical IP achieved in the transition from 45 to 32 nm was up to a:

• 43% decrease in leakage
• 30% decrease in dynamic power for the same performance, and
• 55% area reduction for the same performance

The physical IP products are available today from DesignStart for 32 nm and will be available from multiple foundries at 28nm low power libraries. I shared a table with Simon Segars who tweeted during the lunch that I retweeted:

RT @simonsegars: #ARM has taped out 11 chips on the CP 32/28nm HKMG technology. Design IP available now: http://designstart.arm.com #47DAC

I love when an executive tweets.

Achieve Early Software Development Pre-Silicon with ARM and EDA Tools

I like diversity so after lunch, I was ready to hear about some other ARM products. I headed back to the Cadence booth to hear Vincent Korstanje of our System Design Division discuss the ARM software tools. Vincent (aka, technical guy, see below) discussed how the ARM tools are enabling the software to drive the hardware design rather than the typical hardware to software process today. Now the software engineers can direct and define the hardware teams. A pretty bold statement in the typical DAC hardware crowd, but as EDA360 is promoting software first; the DAC crowd also is changing to include more and more software engineers.

Vincent gave the example of the starting early software development (i.e. pre-silicon) with virtual platforms by having the ARM Fast Models drive (through OSCI’s TLM 2.0 AMBA-PV) the Cadence Incisive simulator.

Vstream, a recent ARM product announcement, allows early software development with verification by connecting Vstream, the ARM software debugger, to the SoC debugger via the Cadence Palladium emulator for emulation-based software development. The combined solution allows accurate, fast and real-time verification and post-silicon debug and can speed up interactive software debugging by up to 15x over a typical JTAG adapter solution. Stop by the Cadence booth (1334) to see the demo. (A demo also is available at the Mentor booth (1383) with the Veloce emulator.)

My favorite tweet: @EDA_360: #ARM technical guy in #EDA360 Theatre at #47DAC says a big benefit of HW-SW co-dev for systems is reduced overdesign

ARM Connected Community Partners

Don’t forget to check out all of the ARM Connected Community at DAC. I hope to find time to visit more of them myself!

Where’s the color commentary? Unfortunately the funny bits that I’d like to add from the evening aren’t suitable for public coverage. Stop me at the show and maybe you can convince me to share a non-PC laugh with you. Wednesday has come all too soon….

Lori Kate Smith, Partnership Marketing Manager, ARM, has the best job at ARM because she gets to work with ARM Partners developing programs that enable broader support for the ARM architecture in her role of managing the ARM Connected Community. She’s passionate about creating communities where engineers can share information, find answers to their questions and talk about cool technologies. Prior to ARM, Lori Kate spent time in multiple different industries including EDA (Cadence, Verisity, Axis Systems), Enterprise Software and dot bomb (HelloBrain), and wireless (Metricom (Ricochet), AT&T, and MCCaw Cellular equally splitting her time between every marketing and buz dev role you can imagine and major account sales. If there’s a new technology to launch or sell, she’s game. Lori Kate even managed to get a few degrees at Santa Clara University (MBA) and Middlebury College (BA.)

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